Appendices

Syntax cheat sheet, reserved words, common conversion functions (numeric_std), operator & attribute quick reference, learning resources and suggested study plan (12 weeks).

Appendices

38.1 Syntax cheat sheet 38.2 Reserved words abs access after alias all and architecture array assert assume attribute begin block body buffer bus case component configuration constant context cover default disconnect downto else elsif end entity exit fairness file for force function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package parameter port postponed private procedure process property protected pure range record register reject release rem report restrict return rol ror select sequence severity shared signal sla sll sra srl strong subtype then to transport type unaffected units until use variable view vmode vprop vunit wait when while with xnor xor

38.3 Common conversion functions (numeric_std) std_logic_vector → unsigned/signed unsigned(v), signed(v)

unsigned/signed → std_logic_vector unsigned/signed → integer integer → unsigned to_unsigned(i, width) integer → signed to_signed(i, width) std_logic_vector → integer integer → std_logic_vector

std_logic_vector(to_unsigned(i, width)) resize(u, new_width) boolean → std_logic '1' when b else '0' std_logic → boolean s = '1' or ?? s (2008)

to_string(x), to_hstring(v), integer'image(i) 38.4 Operator & attribute quick reference

and or nand nor xor xnor not = /= < <= > >= ?= + - * / mod rem ** abs & sll srl rol ror

'length 'range 'reverse_range 'high 'low 'left 'right 'event 'image 'value 'pos 'val 'succ 'pred 'last_value 'stable rising_edge(clk), falling_edge(clk) 38.5 Learning resources

*Free Range VHDL* — Bryan Mealy & Fabrizio Tappero (free) *The Designer's Guide to VHDL* (3rd ed.) — Peter Ashenden

*VHDL-2008: Just the New Stuff* — Peter Ashenden & Jim Lewis

*RTL Hardware Design Using VHDL* — Pong P. Chu *FPGA Prototyping by VHDL Examples* — Pong P. Chu

*Digital Design and Computer Architecture* — Harris & Harris (VHDL/SystemVerilog editions)

*Effective Coding with VHDL* — Ricardo Jasinski *Circuit Design and Simulation with VHDL* — Volnei Pedroni *Advanced FPGA Design* — Steve Kilts

Online: nandland.com, VHDLwhiz, fpga4fun, FPGA Tutorial (fpgatutorial.com), Digi-Key/AMD/Intel training, EDA Playground, osvvm.org, uvvm.org, vunit.github.io, docs.cocotb.org, GHDL & NVC documentation, OpenCores, Hackaday FPGA projects

Boards for learning: Digilent Basys 3 / Arty A7 / Nexys A7 (AMD), Terasic DE10-Lite / DE1-SoC (Intel), iCEBreaker / Tang Nano / ULX3S (open-source toolchain friendly), Zynq boards (PYNQ-Z2, ZedBoard) for HW/SW co-design

Community: r/FPGA, EEVblog forum, Stack Exchange (Electrical Engineering), FPGA Discord servers, IEEE VHDL Analysis and Standardization Group (VASG) 38.6 Suggested study plan (12 weeks)

Digital logic refresher, tools, first entity/architecture, libraries

Types, objects, operators, attributes — Part I exercises Concurrent vs sequential statements, simulation semantics

Combinational & sequential logic — blinky on real hardware FSMs, structural design, generics, generate — Project 1

Subprograms, packages, testbenches, TEXTIO — Part II exercises VHDL-2008/2019, memories, FIFOs

Arithmetic, fixed point, DSP, synthesis rules FPGA architecture, timing constraints, CDC — Project 2 UART, SPI, I2C, VGA, AXI — Project 3

Advanced verification (OSVVM/UVVM/VUnit/cocotb), formal, IP integration

Complete projects, CPU design, best practices — Project 5 or 6 🎓 Final Words

You've learned to think in hardware: from a single AND gate to FSMs, memories, DSP pipelines, clock-domain crossings, bus protocols, verification methodologies, and a working CPU. Simulate everything, constrain every clock, synchronize every asynchronous signal, and verify before you synthesize. Get an FPGA board, build the projects, and watch your VHDL come alive in silicon. Happy designing! ⚡

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity name is
  generic (N : positive := 8);
  port (
    clk, rst : in  std_logic;
    din      : in  std_logic_vector(N-1 downto 0);
    dout     : out std_logic_vector(N-1 downto 0));
end entity;

architecture rtl of name is
  type state_t is (IDLE, RUN);
  signal state : state_t := IDLE;
  signal cnt   : unsigned(N-1 downto 0) := (others => '0');
  constant MAX : natural := 100;
begin
  -- concurrent
  y <= a and b;
  y <= a when sel = '1' else b;
  with sel select y <= a when "00", b when "01", c when others;

  -- sequential (clocked)
  p_reg : process (clk)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        cnt <= (others => '0');
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;

  -- combinational
  p_comb : process (all)
  begin
    dout <= (others => '0');
    case state is
      when IDLE => null;
      when RUN  => dout <= std_logic_vector(cnt);
    end case;
  end process;

  -- instance & generate
  u_sub : entity work.sub generic map (W => N) port map (clk => clk, d => din, q => open);
  g_loop : for i in 0 to N-1 generate
    q(i) <= d(N-1-i);
  end ge
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