Capstone Projects

Seven-segment display, button-controlled time setting (debounced), alarm comparison, buzzer PWM.

Project 1 — Digital clock with alarm (beginner)

Seven-segment display, button-controlled time setting (debounced), alarm comparison, buzzer PWM. *Concepts: counters, FSMs, debouncing, multiplexed displays.*

Project 2 — UART-controlled LED & register system (beginner/intermediate)

PC sends commands over UART (W addr data, R addr); FPGA parses, writes/reads a register file, responds; full testbench with a UART BFM. *Concepts: UART RX/TX, FIFOs, parsers, BFMs.*

Project 3 — VGA game (intermediate)

Pong or Snake on a VGA monitor with keyboard (PS/2) or button input, sprites, score display, sound. *Concepts: video timing, ROMs, collision logic, hierarchy.*

Project 4 — DSP audio processor (advanced)

I2S audio codec interface, FIR/IIR filters in fixed point, volume control and echo effect using block RAM delay lines; verify against a Python model. *Concepts: fixed point, DSP blocks, pipelining, memories, CDC.*

Project 5 — AXI-based SoC peripheral (advanced)

An AXI4-Lite controlled PWM/timer or an AXI-Stream image filter (e.g., Sobel edge detection) integrated with a Zynq processor or soft RISC-V core; Linux or bare-metal driver. *Concepts: AXI protocols, register maps, HW/SW co-design.*

Project 6 — RISC-V CPU (expert)

Implement RV32I (multi-cycle, then 5-stage pipelined) in VHDL, verify with official RISC-V compliance tests, run C programs, add UART/GPIO peripherals. *Concepts: datapath/control design, pipelining, hazards, verification at scale.*

Project 7 — High-speed data acquisition (expert)

SPI/LVDS ADC capture, asynchronous FIFOs across clock domains, triggering logic, DMA to DDR memory, and Ethernet/UDP streaming to a PC. *Concepts: CDC, timing closure, high-throughput design, IP integration.*

Project 8 — Verification showcase (expert)

Build a complete OSVVM/UVVM or cocotb environment for a FIFO or AXI peripheral: constrained-random stimulus, scoreboards, functional coverage closure, formal properties, and a CI regression. *Concepts: advanced verification methodology.*