Concurrent Statements

Statements in an architecture body (outside processes) execute concurrently — order doesn't matter.

Statements in an architecture body (outside processes) execute concurrently — order doesn't matter. Each describes hardware that is always active.

9.1 Simple signal assignment

y <= a and b;
sum <= a xor b xor cin;
z <= not x after 2 ns;        -- delay (simulation only; ignored by synthesis)

9.2 Conditional signal assignment (when ... else) — priority logic

y <= a when sel = "00" else
     b when sel = "01" else
     c when sel = "10" else
     d;

grant <= "100" when req(2) = '1' else      -- priority encoder
         "010" when req(1) = '1' else
         "001" when req(0) = '1' else
         "000";

9.3 Selected signal assignment (with ... select) — parallel multiplexer

VHDL-2008 adds matching versions with sel select? (allowing '-' don't-cares).

with sel select
  y <= a when "00",
       b when "01",
       c when "10",
       d when others;          -- 'others' required to cover all std_logic values

with opcode select
  result <= x + y when OP_ADD,
            x - y when OP_SUB,
            x and y when OP_AND,
            (others => '0') when others;

9.4 Concurrent assertions & procedure calls

assert not (wr_en = '1' and rd_en = '1') report "simultaneous read/write" severity warning;

9.5 Block statements

b1 : block
  signal tmp : std_logic;
begin
  tmp <= a and b;
  y <= tmp or c;
end block b1;

9.6 Generate statements (covered in §15)

for ... generate, if ... generate, case ... generate (2008) replicate or conditionally create hardware.