Data Types

VHDL is strongly typed — no implicit conversion between types.

VHDL is strongly typed — no implicit conversion between types.

5.1 Predefined scalar types (package std.standard)

rarely used in practice false, true at least −2³¹+1.. 2³¹−1 (64-bit in VHDL-2019) use ranges for synthesis 0.. integer'high 1.. integer'high simulation only (not synthesizable) ASCII/ISO-8859-1 characters physical type: fs, ps, ns, us, ms, sec, min, hr note, warning, error, failure

5.2 std_logic — the 9-valued logic (IEEE 1164)

uninitialized (default) forcing unknown (conflict) high impedance (tri-state) weak 0 (pull-down) weak 1 (pull-up)

std_logic is a resolved type: multiple drivers are combined by a resolution function (e.g., '0' and '1' → 'X'). std_ulogic is the unresolved base type (catches multiple-driver bugs at compile time). In VHDL-2008 std_logic_vector is a resolved subtype of std_ulogic_vector.

signal enable : std_logic;
signal data   : std_logic_vector(7 downto 0);   -- 8-bit bus, MSB first
signal addr   : std_logic_vector(0 to 15);      -- ascending range (less common)
data <= x"A5";
data <= (others => '0');                        -- aggregate: all zeros
data <= (7 => '1', others => '0');              -- MSB set
enable <= data(3);                              -- bit select
data(3 downto 0) <= "1111";                     -- slice

5.3 numeric_std: unsigned & signed

use ieee.numeric_std.all;
signal u : unsigned(7 downto 0);     -- 0 .. 255
signal s : signed(7 downto 0);       -- -128 .. 127 (two's complement)
u <= u + 1;                           -- arithmetic defined for unsigned/signed
s <= -s;
u <= to_unsigned(200, 8);
s <= to_signed(-5, 8);

5.4 Type conversions (the "conversion triangle")

signal slv : std_logic_vector(7 downto 0);
signal u   : unsigned(7 downto 0);
signal s   : signed(7 downto 0);
signal i   : integer range 0 to 255;

u   <= unsigned(slv);                 -- type cast (closely related types)
s   <= signed(slv);
slv <= std_logic_vector(u);
i   <= to_integer(u);                 -- unsigned → integer
u   <= to_unsigned(i, u'length);      -- integer → unsigned (needs size)
slv <= std_logic_vector(to_unsigned(i, 8));
i   <= to_integer(unsigned(slv));
s16 <= resize(s, 16);                 -- resize: sign-extends signed, zero-extends unsigned (s16 : signed(15 downto 0))

std_logic_vector
          ↗ cast        cast ↖
     unsigned  ←→  signed (casts)
          ↘ to_integer / to_unsigned / to_signed ↙
                   integer

5.5 Enumerated types

type state_t is (IDLE, LOAD, RUN, DONE);
signal state : state_t := IDLE;
type color_t is (RED, GREEN, BLUE);

5.6 Integer ranges & subtypes

signal count : integer range 0 to 99;        -- synthesizes to 7 bits
subtype byte_t is std_logic_vector(7 downto 0);
subtype small_int is integer range -8 to 7;

5.7 Arrays

type mem_t is array (0 to 255) of std_logic_vector(7 downto 0);  -- constrained array (memory)
signal ram : mem_t;
type matrix_t is array (0 to 3, 0 to 3) of integer;               -- 2-D
type slv_array is array (natural range <>) of std_logic_vector;   -- unconstrained (VHDL-2008 element too)
signal regs : slv_array(0 to 7)(31 downto 0);
ram(10) <= x"3C";
ram(10)(7) <= '1';                                                -- bit of an element

5.8 Records

type pixel_t is record
  r, g, b : unsigned(7 downto 0);
  valid   : std_logic;
end record;
signal px : pixel_t;
px.r <= x"FF";
px <= (r => x"10", g => x"20", b => x"30", valid => '1');

5.9 Physical, access, file & protected types

type distance is range 0 to 1e9 units mm; cm = 10 mm; m = 1000 mm; end units;  -- physical
type int_ptr is access integer;              -- pointer (simulation only)
type text_file is file of string;            -- file type
type counter_pt is protected                 -- shared state with methods (simulation/verification)
  procedure inc; impure function get return integer;
end protected;