Lexical Elements, Libraries & Packages

4.1 Lexical rules

Case-insensitive: SIGNAL, Signal, signal are identical (convention: lowercase keywords).

Comments: -- single line; /* ... */ block comments (VHDL-2008).

Statements end with ;.

Identifiers: letters, digits, single underscores; must start with a letter; no trailing/double underscores. Extended identifiers: \my signal\.

'0' '1' 'Z' 'X'             -- character literals (std_logic values)
"1010"                      -- bit string
x"FF"  o"17"  b"1010_1010"  -- hex, octal, binary strings (underscores allowed)
8x"FF"  12d"100"  4sx"F"    -- sized & signed bit strings (VHDL-2008)
42  16#2A#  2#101010#       -- integers in various bases
3.14  1.0e-3                -- reals
10 ns  5 us  2 ms  1 sec    -- physical (time) literals
"Hello"                     -- string

4.2 Libraries & use clauses

work — the current library (where your design units are compiled).

std — always visible: standard package (bit, boolean, integer, real, time, character, string).

⚠️ Avoid non-standard Synopsys packages std_logic_arith, std_logic_unsigned, std_logic_signed — use numeric_std.

library ieee;                          -- make the library visible
use ieee.std_logic_1164.all;           -- std_logic, std_logic_vector
use ieee.numeric_std.all;              -- unsigned, signed, arithmetic (the STANDARD choice)
use ieee.math_real.all;                -- real math (simulation / constants only)
use ieee.fixed_pkg.all;                -- fixed point (VHDL-2008)
use ieee.float_pkg.all;                -- floating point (VHDL-2008)
use std.textio.all;                    -- file I/O
use std.env.all;                       -- stop, finish (VHDL-2008)

4.3 Context declarations (VHDL-2008)

context project_ctx is
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
end context;

-- in other files:
library work;
context work.project_ctx;