What Is SystemVerilog?

One language for designing hardware and for verifying it: Verilog plus modern design constructs plus a full verification language.

SystemVerilog (IEEE 1800) is a superset of Verilog. Every Verilog-2005 design is valid SystemVerilog, and the language adds two large groups of features: better design constructs (logic, enums, structs, interfaces, packages, always_comb/always_ff) and a complete verification language (classes, constrained-random stimulus, functional coverage, assertions, processes and mailboxes). It is the standard language of chip design and verification today.

Tools used in this course

Learning SystemVerilog as "Verilog with classes" and skipping the design features

Use logic, enums, structs, always_comb/always_ff and interfaces in every new RTL design

The design improvements remove whole classes of Verilog bugs (accidental latches, wrong sensitivity lists, mismatched bus connections). Interviews for RTL roles expect them.

Is every Verilog design valid SystemVerilog?

Almost always: SystemVerilog is a superset of Verilog-2005. The rare exceptions are Verilog identifiers that became SystemVerilog keywords (for example a signal named logic, bit or class).

Which parts of SystemVerilog can be synthesized?

The design subset: logic and other data types, enums, packed structs and unions, packed arrays, interfaces and modports, packages, functions, always_comb/always_ff/always_latch, unique/priority case. Classes, dynamic arrays, queues, randomization, coverage and most assertions are for simulation (assertions are also used by formal tools).