Data Types: logic, bit, int & Friends

4-state and 2-state types, the fixed-width integer types, typedef and casting.

SystemVerilog replaces Verilog's confusing reg/wire choice with logic, and adds 2-state types for fast testbench code. Choosing the right type matters: 4-state types show X when something is wrong; 2-state types hide it.

Integer sizes, typedef and casts

bit [7:0] status = dut.status; // in the testbench logic [7:0] status = dut.status;

A 2-state variable turns an X from an unreset register into 0, so the bug disappears from your checks. Sample design signals into 4-state variables.

logic [7:0] count; for (count = 0; count < 256; count++) ...

for (int i = 0; i < 256; i++) ...

An 8-bit counter can never reach 256, so the loop never ends. Use an int loop variable.

What is the default value of an int and of a logic variable at time 0?

int (2-state) starts at 0; logic (4-state) starts at X.

Which types are signed by default?

byte, shortint, int, longint and integer. bit, logic and reg are unsigned unless declared signed.

bit [3:0] b; logic [3:0] l = 4'b10xz; b = l; What is b?

4'b1000: the X and Z bits become 0 in a 2-state variable.