Thyristor Family: SCR, TRIAC, DIAC, GTO & IGCT

Latching PNPN devices. Learn the four-layer structure and two-transistor model, regenerative latching (α₁ + α₂ ≥ 1), forward blocking, forward conduction and reverse blocking, gate triggering, latching and holding currents, turn-off by commutation (natural and forced), dv/dt and di/dt limits, TRIAC bidirectional operation and triggering quadrants, DIAC breakover triggering, gate turn-off thyristors (GTO) and integrated gate-commutated thyristors (IGCT), the UJT concept, and applications from dimmers to HVDC — with Python checking latching conditions, dv/dt-induced false triggering and phase-control power.

A thyristor is a PNPN structure that behaves like two cross-coupled transistors: once triggered, each supplies the other's base current and the device latches on until its current falls below the holding level.

That makes thyristors extremely efficient, rugged high-power switches for AC control and very high voltage/current conversion — but they cannot simply be turned off by the gate (except GTOs and IGCTs).

An analogy

A thyristor is like a mousetrap: a small nudge (gate pulse) springs it shut, and it stays shut no matter what you do to the trigger — only removing the load (current below holding) resets it.

SCR operation

Key behaviours:

TRIAC and DIAC

A TRIAC is effectively two anti-parallel SCRs with one gate, conducting in both directions — ideal for AC dimmers, fan speed control and solid-state relays. It can be triggered in four quadrants (MT2 ± with gate ±); quadrants I and III are most sensitive, IV often avoided. 'Snubberless' TRIACs tolerate higher commutating dv/dt with inductive loads. A DIAC is a bidirectional breakover device (~30 V) used to give TRIAC gates a sharp trigger pulse from an RC phase-shift network.

GTO and IGCT

GTOs (gate turn-off thyristors) have interdigitated gate-cathode structures so a large negative gate current (one-third to one-fifth of anode current) can pull carriers out and turn the device off; they need bulky snubbers. IGCTs integrate a very low-inductance gate driver that commutates the entire cathode current to the gate within ~1 µs, turning the device off like a transistor (snubberless) — used in MV drives and HVDC. The UJT (unijunction transistor) is a historical relaxation-oscillator trigger device.

Ratings and protection

Voltage ratings V_DRM/V_RRM, surge current I_TSM and I²t (fuse coordination), di/dt at turn-on (current must spread from the gate region — limit with series inductance), dv/dt (RC snubbers, gate-cathode resistors), and thermal ratings. Press-pack thyristors reach 8–10 kV and several kA per device.

Formulas

Worked example: Anode current

Given: α₁ 0.4, α₂ 0.5, I_G 10 mA, I_CO ≈ 0

Find: I_A (before latching).

Answer: 50 mA — gains rise with current → latches

Worked example: Half power angle

Given: Resistive AC load

Find: Firing angle for 50% power.

Answer: 90°

Worked example: Snubber check

Given: C_j 50 pF, I_trigger 5 mA

Find: Max safe dv/dt.

Answer: 100 V/µs

SCR structure and two-transistor model

  Anode ── p⁺ ── n⁻ ── p ── n⁺ ── Cathode          PNP (Q1): p⁺ n⁻ p
                   J1    J2    J3                   NPN (Q2): n⁻ p n⁺
                          ▲ Gate (p base)           Q1 collector → Q2 base, Q2 collector → Q1 base
  Forward blocking: J2 reverse-biased blocks voltage;  gate current → Q2 on → Q1 on → regenerative latch
  I–V: forward blocking → breakover → low-voltage on-state (≈ 1–2 V); reverse: blocks like a diode

In forward blocking only the middle junction J2 is reverse-biased. Gate current turns on the NPN, whose collector current is the PNP's base current, which feeds the NPN base further. When the sum of gains reaches 1 the device latches and both sides flood with carriers (very low on-state voltage).

Latching, dv/dt and phase control

import math
# Thyristor: two-transistor latching, dv/dt triggering, phase-control power
for a1, a2 in ((0.3, 0.4), (0.5, 0.45), (0.6, 0.45)):
    s = a1 + a2
    print(f"alpha1 = {a1}, alpha2 = {a2}: sum = {s:.2f} -> {'LATCHES (regenerative)' if s >= 1 else 'no latch'}")
Cj, dvdt, Igt = 30e-12, 500e6, 10e-3
Idisp = Cj * dvdt
print(f"displacement current Cj*dv/dt = {Idisp*1e3:.1f} mA vs gate trigger {Igt*1e3:.0f} mA -> {'false triggering!' if Idisp >= Igt else 'safe'}")
Vrms, R = 230.0, 20.0
for deg in (0, 60, 90, 120):
    a = math.radians(deg)
    frac = 1 - a / math.pi + math.sin(2 * a) / (2 * math.pi)     # AC phase control (TRIAC), fraction of full power
    print(f"firing angle {deg:3d} deg: load power {Vrms**2/R*frac:7.1f} W ({frac*100:5.1f}%)")
# alpha1 = 0.3, alpha2 = 0.4: sum = 0.70 -> no latch
# alpha1 = 0.5, alpha2 = 0.45: sum = 0.95 -> no latch
# alpha1 = 0.6, alpha2 = 0.45: sum = 1.05 -> LATCHES (regenerative)
# displacement current Cj*dv/dt = 15.0 mA vs gate trigger 10 mA -> false triggering!
# firing angle   0 deg: load power  2645.0 W (100.0%)
# firing angle  60 deg: load power  2127.9 W ( 80.4%)
# firing angle  90 deg: load power  1322.5 W ( 50.0%)
# firing angle 120 deg: load power   517.1 W ( 19.6%)

The loop gain condition α₁ + α₂ ≥ 1 decides latching; gains rise with current, which is why a minimum latching current exists. A fast 500 V/µs edge through 30 pF of junction capacitance injects 15 mA — enough to trigger a sensitive-gate device falsely, hence snubbers and gate-cathode resistors. Phase control of a 20 Ω heater on 230 V delivers 50% power at a 90° firing angle.

Common mistakes

Applications

Key takeaways

Going further