Semiconductor Memory: SRAM, DRAM, ROM, EEPROM & Flash

How chips store bits. Learn SRAM (6T cell of cross-coupled inverters, read/write, static noise margin, stability vs sizing, leakage), DRAM (1T1C cell, charge storage, charge sharing onto bit lines, sense amplifiers, refresh and retention, trench vs stacked capacitors, row-hammer), ROM family (mask ROM, PROM, EPROM, EEPROM), and flash (floating-gate and charge-trap cells, NAND vs NOR arrays, program/erase, MLC/TLC/QLC multi-level storage, endurance and retention, 3D NAND) — with Python computing DRAM electrons, bit-line signal, retention and refresh margin, flash V_T shift per electron and multi-level spacing.

Memory is the majority of all transistors ever made. Each memory type trades speed, density, cost, volatility and endurance differently: SRAM is fast but large, DRAM dense but must be refreshed, flash non-volatile but slow to write and wears out.

At the device level, every memory stores a bit as a state of a transistor circuit, a charge on a capacitor, or charge trapped near a transistor channel.

An analogy

SRAM is a light switch that stays wherever you flip it (while powered). DRAM is a leaky bucket that must be topped up regularly (refresh). Flash is a sealed jar: filling or emptying it takes effort (high voltage), but it keeps its contents for years without power.

SRAM

Two cross-coupled inverters hold the state; access transistors connect it to bit lines. Read stability requires strong pull-downs relative to access devices (cell ratio); writability requires access devices stronger than pull-ups (pull-up ratio). Static noise margin shrinks with lower V_DD and variability, limiting minimum operating voltage (V_min). SRAM leakage matters in large caches (sleep modes, retention voltage).

DRAM

Key points:

ROM, EPROM, EEPROM

Mask ROM fixes data during fabrication; PROM uses one-time fuses/antifuses; EPROM programs floating gates by hot-electron injection and erases with UV light; EEPROM uses Fowler-Nordheim tunnelling through thin oxide for byte-level electrical erase (more transistors per bit, high endurance ~10⁶ cycles).

Flash: NOR, NAND, 3D

NOR flash connects cells in parallel (fast random read, execute-in-place code storage). NAND flash connects cells in series strings (smallest cell, page read/program, block erase — SSDs, phones). Programming uses high voltage (~15–20 V) FN tunnelling (NAND) or hot-electron injection (NOR); incremental step-pulse programming with verify places V_T precisely. 3D NAND stacks 200+ layers of charge-trap cells vertically. Endurance: SLC ~10⁵, MLC ~10⁴, TLC ~3000, QLC ~1000 P/E cycles; controllers use ECC, wear levelling and over-provisioning.

Formulas

Worked example: Bit-line signal

Given: C_s 25 fF, C_BL 150 fF, V_DD 1.1 V

Find: ΔV.

Answer: 79 mV

Worked example: Electrons per level

Given: C_pp 0.1 fF, spacing 0.4 V

Find: Electrons.

Answer: ≈ 250 electrons

Worked example: TLC levels

Given: 3 bits/cell

Find: V_T states.

Answer: 8

6T SRAM, 1T1C DRAM, floating-gate flash

  6T SRAM                    1T1C DRAM                  Floating-gate flash
  BL ─ access ─┐ ┌─ access ─ BLB   WL                         control gate
       inv ◄──►inv (latch)          │                          ═══ ONO dielectric
  WL controls both access TFTs  BL ─┤ access NMOS ─ C_s ─ plate ═══ floating gate (charge!)
  Q and Q̄ held by feedback           charge = bit (leaks)      ─── tunnel oxide (~8 nm)
                                                              S ▓ channel ▓ D (V_T shifts)

SRAM stores the bit in a bistable latch (six transistors, no refresh). DRAM stores it as charge on a small capacitor accessed through one transistor — dense but leaky and destructively read. Flash stores electrons on an isolated floating gate (or in a nitride trap layer), shifting the transistor's threshold; it keeps data without power.

DRAM signal and retention; flash V_T per electron

# Memory cells: DRAM storage, retention and refresh; flash threshold shift and multi-level storage
q = 1.602e-19
Cs, V = 20e-15, 1.0
print(f"DRAM cell 20 fF at 1 V stores {Cs*V/q:.0f} electrons")
Cbl = 100e-15
print(f"charge sharing onto 100 fF bit line: signal {V/2*Cs/(Cs+Cbl)*1e3:.0f} mV around VDD/2 (sense-amp input)")
Ileak = 1e-15
t_ret = Cs * 0.3 / Ileak
print(f"leakage 1 fA, 0.3 V allowed loss: retention {t_ret*1e3:.0f} ms -> refresh every 64 ms gives margin {t_ret/0.064:.0f}x")
print(f"at 85 C leakage ~x10: retention {t_ret/10*1e3:.0f} ms (why hot DRAM refreshes at 32 ms)")
Cpp = 0.1e-15                                      # control-gate-to-floating-gate capacitance of a scaled cell
for ne in (100, 1000):
    print(f"flash: {ne} electrons on the floating gate -> Vt shift {ne*q/Cpp:.2f} V")
for bits in (1, 2, 3, 4):
    levels = 2 ** bits
    print(f"{bits} bit/cell: {levels} Vt levels in a 6 V window -> spacing {6/(levels-1):.2f} V")
# DRAM cell 20 fF at 1 V stores 124844 electrons
# charge sharing onto 100 fF bit line: signal 83 mV around VDD/2 (sense-amp input)
# leakage 1 fA, 0.3 V allowed loss: retention 6000 ms -> refresh every 64 ms gives margin 94x
# at 85 C leakage ~x10: retention 600 ms (why hot DRAM refreshes at 32 ms)
# flash: 100 electrons on the floating gate -> Vt shift 0.16 V
# flash: 1000 electrons on the floating gate -> Vt shift 1.60 V
# 1 bit/cell: 2 Vt levels in a 6 V window -> spacing 6.00 V
# 2 bit/cell: 4 Vt levels in a 6 V window -> spacing 2.00 V
# 3 bit/cell: 8 Vt levels in a 6 V window -> spacing 0.86 V
# 4 bit/cell: 16 Vt levels in a 6 V window -> spacing 0.40 V

A 20 fF DRAM cell holds ~125 000 electrons, but charge sharing with a 100 fF bit line leaves only ~83 mV for the sense amplifier. With 1 fA of leakage the cell keeps data ~6 s — ample margin for 64 ms refresh at room temperature, less when hot. In a scaled flash cell each ~100 electrons move V_T by ~0.16 V, so QLC (16 levels, 0.4 V spacing) distinguishes differences of just a few hundred electrons — which is why endurance and retention fall with more bits per cell.

Common mistakes

Applications

Key takeaways

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