Silicon Crystal Growth, Wafers & Epitaxy

Where every chip begins. Follow the complete fabrication flow overview (raw silicon → crystal growth → wafering → front-end processing → test → packaging), then learn polysilicon purification, Czochralski (Cz) and float-zone (FZ) growth, dopant segregation and oxygen in Cz silicon, ingot orientation, wafer diameter and thickness, sawing, lapping, polishing (CMP) and cleaning (RCA), surface quality and wafer defects, and epitaxy — homo- and heteroepitaxy by CVD and MBE, doping and thickness control, crystal quality, and its role in CMOS, power, RF and optoelectronic devices — with Python computing Cz segregation profiles, dies per wafer for 200/300 mm, and epitaxy times.

Semiconductor manufacturing starts with sand and ends with near-perfect single-crystal wafers containing fewer than one unwanted impurity per billion atoms. Wafer quality sets defect density, lifetime and ultimately yield.

Epitaxy then grows new crystalline layers with precisely controlled doping — the starting point for power devices, bipolar transistors, lasers and HEMTs.

An analogy

Growing a silicon ingot is like pulling a perfect candle out of molten wax with a single-crystal 'seed' as the wick: pull too fast or disturb the melt and the structure breaks into grains.

Crystal growth

Two methods:

Wafering

Ingots are ground to diameter, orientation-marked with a notch (300 mm) or flats, sliced by wire saws, lapped, etched to remove damage, and chemically-mechanically polished to atomic-level flatness (nm roughness, µm total thickness variation). RCA cleaning (SC-1 for particles/organics, SC-2 for metals, HF dips for oxide) keeps metallic contamination below 10¹⁰ atoms/cm². Thickness: 725 µm (200 mm) and 775 µm (300 mm); thinned later for packaging and power devices.

Epitaxy

Epitaxy grows a crystalline layer that continues the substrate lattice. Silicon CVD epitaxy (SiH₄, SiH₂Cl₂, SiHCl₃ at 1000–1200 °C) provides lightly doped layers on heavily doped substrates (power MOSFETs, BJTs, latch-up-resistant CMOS). Heteroepitaxy (SiGe on Si, GaN on Si/SiC/sapphire, InGaAs on InP) creates heterojunctions; mismatch causes strain or dislocations. MOCVD and MBE grow III-V quantum wells for lasers and HEMTs with atomic-layer control. Selective epitaxy grows raised source/drains and SiGe stressors in CMOS.

Wafer defects and specifications

Crystal-originated particles (COPs), oxygen precipitates, slip lines from thermal stress, stacking faults and epitaxial defects all reduce yield. Wafer specs list diameter, orientation, dopant and resistivity range, oxygen/carbon content, flatness (site flatness for lithography), particles, and metal contamination. SOI wafers (Smart Cut) and engineered substrates add further specifications.

Formulas

Worked example: Segregation

Given: P, k₀ 0.35, C₀ 10¹⁵, f 0.5

Find: C_s.

Answer: 5.5 × 10¹⁴ cm⁻³

Worked example: Dies per wafer

Given: 300 mm, 25 mm² die

Find: DPW.

Answer: ≈ 2694

Worked example: Mismatch

Given: Si₀.₇Ge₀.₃ (a ≈ 5.498 Å) on Si

Find: f.

Answer: ≈ 1.2% (compressive strain)

Complete fabrication flow

  Raw silicon (quartz → MG-Si → trichlorosilane → electronic-grade polysilicon, 11N)
    → Crystal growth (Cz / FZ ingot) → Wafer slicing → Lapping/Polishing (CMP) → Cleaning (RCA)
    → Oxidation → Deposition → Photolithography → Etching → Doping/Implantation → Annealing
       (repeated 20–80+ mask layers in the front end)
    → Metallization (back end of line, 10–20 metal layers) → Passivation
    → Wafer test (probe) → Dicing → Packaging → Final test & burn-in

The front end of line (FEOL) builds transistors in the silicon; the back end of line (BEOL) builds the multilevel interconnect. A modern logic process uses hundreds of individual steps and many weeks of cycle time; wafer test and final test screen defective dies.

Segregation, dies per wafer and epitaxy time

import math
# Czochralski dopant segregation along the ingot, dies per wafer, epitaxial growth time
C0 = 1e15
for name, k in (("boron", 0.8), ("phosphorus", 0.35)):
    vals = [k * C0 * (1 - f) ** (k - 1) for f in (0.0, 0.5, 0.9)]
    print(f"{name:10s} (k = {k}): Cs at 0%, 50%, 90% solidified = " + ", ".join(f"{v:.2e}" for v in vals))
def dies_per_wafer(D_mm, die_mm2):
    return math.pi * (D_mm / 2) ** 2 / die_mm2 - math.pi * D_mm / math.sqrt(2 * die_mm2)
for D in (200, 300):
    print(f"{D} mm wafer, 100 mm^2 die: ~{dies_per_wafer(D, 100):.0f} gross dies (area ratio {(D/200)**2:.2f}x)")
rate = 1.0                                   # um/min typical silicon CVD epitaxy
print(f"10 um Si epi layer at {rate} um/min: {10/rate:.0f} min; SiC epi grows ~10 um/h -> a 30 um drift layer for 3.3 kV takes ~{30/10:.0f} h")
# boron      (k = 0.8): Cs at 0%, 50%, 90% solidified = 8.00e+14, 9.19e+14, 1.27e+15
# phosphorus (k = 0.35): Cs at 0%, 50%, 90% solidified = 3.50e+14, 5.49e+14, 1.56e+15
# 200 mm wafer, 100 mm^2 die: ~270 gross dies (area ratio 1.00x)
# 300 mm wafer, 100 mm^2 die: ~640 gross dies (area ratio 2.25x)
# 10 um Si epi layer at 1.0 um/min: 10 min; SiC epi grows ~10 um/h -> a 30 um drift layer for 3.3 kV takes ~3 h

Because dopants prefer the melt (k₀ < 1), their concentration rises along the ingot: phosphorus (k₀ 0.35) varies 4.5× from seed to tail, boron (0.8) only 1.6× — why boron-doped Cz wafers have tighter resistivity specs. A 300 mm wafer offers 2.25× the area of a 200 mm wafer but ~2.4× the dies (less edge loss). SiC's slow epitaxy makes thick high-voltage layers expensive.

Common mistakes

Applications

Key takeaways

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