JFET Physics: Channel, Pinch-off & the Shockley Equation

The junction field-effect transistor from the inside. Learn N- and P-channel construction, the gate PN junction controlling channel thickness, depletion from gate voltage and drain voltage, pinch-off and current saturation, the internal pinch-off voltage V_P0 = qN_Da²/(2ε), V_GS(off), I_DSS and open-channel conductance, the Shockley square-law approximation, output and transfer characteristics, small-signal g_m, r_o and capacitances, low-noise and high-input-impedance properties, temperature behaviour (zero-TC point) and applications — with Python deriving pinch-off voltage, I_DSS, I_D and g_m from doping and geometry.

A JFET is a doped semiconductor bar whose cross-section is squeezed by reverse-biased gate junctions. More reverse gate voltage → wider depletion → narrower channel → less current. It is a normally-on, voltage-controlled resistor and current source.

Its gate is a reverse-biased junction (pA leakage) and its channel has no oxide interface — making JFETs exceptionally quiet at low frequencies, prized in audio and instrumentation.

An analogy

A JFET is a garden hose with a clamp: the gate voltage tightens the clamp (depletion), the water flow (drain current) drops, and eventually the hose is pinched shut. Pushing harder at the tap (drain voltage) also narrows the downstream end — the flow saturates.

Operation

At V_GS = 0 the channel is open (depletion-mode, normally on). Making V_GS negative (N-channel) widens the gate depletion regions and increases channel resistance. At V_GS = V_P the channel closes completely. For V_DS beyond V_GS − V_P, the channel pinches off at the drain end and I_D saturates.

Characteristics and parameters

Datasheet essentials:

Temperature and zero-TC bias

Mobility falls with temperature (I_D decreases) while V_P magnitude increases slightly (I_D increases); at one bias point near V_GS ≈ V_P + 0.63 V the effects cancel — the zero-temperature-coefficient point used in stable current sources. JFETs also make simple two-terminal current regulators (gate tied to source).

Variants

MESFETs replace the PN gate with a Schottky gate (GaAs RF amplifiers), and SiC JFETs serve as rugged power switches (normally-on, often cascoded with a low-voltage MOSFET to make a normally-off 'SiC cascode'). JFET-input op-amps combine JFET inputs with bipolar gain stages.

Formulas

Worked example: Drain current

Given: I_DSS 12 mA, V_P −3 V, V_GS −1.5 V

Find: I_D.

Answer: 3 mA

Worked example: Transconductance

Given: Same bias

Find: g_m.

Answer: 4 mS

Worked example: Pinch-off

Given: N_D 5 × 10¹⁵, a 1.5 µm

Find: V_P0.

Answer: ≈ 8.7 V

N-channel JFET cross-section

        Gate (p⁺)
   ─────┬─────────────┬─────
  S ═══ │▒▒ depletion ▒│ ═══ D      V_DS > 0: depletion wider near drain (more reverse bias)
        │ n channel ─► │           Pinch-off when depletion meets at the drain end
   ─────┴─────────────┴─────       V_DS(sat) = V_GS − V_P
        Gate (p⁺, tied)

The gate junctions deplete the channel from both sides. With drain voltage the channel potential rises toward the drain, so depletion is wedge-shaped. When the wedges touch at the drain end the channel pinches off; further V_DS drops across the pinched region and the current saturates.

Pinch-off, I_DSS and the transfer curve from physics

import math
# JFET from physics: pinch-off voltage from channel doping and thickness, IDSS, Shockley curve, gm
q, eps = 1.602e-19, 11.7 * 8.854e-14
Nd, a = 1e16, 1.0e-4                       # channel doping, half-thickness 1 um
Vp0 = q * Nd * a**2 / (2 * eps)             # internal pinch-off voltage
Vbi = 0.8
Vp = Vbi - Vp0
print(f"internal pinch-off {Vp0:.2f} V -> VGS(off) = Vbi - Vp0 = {Vp:.2f} V")
mu, Z, L = 1100.0, 1000e-4, 10e-4           # mobility, width 1 mm, length 10 um
G0 = q * Nd * mu * 2 * a * Z / L
print(f"open-channel conductance G0 = {G0*1e3:.2f} mS (R0 = {1/G0:.0f} ohm)")
IDSS = G0 * Vp0 / 3                         # square-law approximation of the full Shockley model
print(f"IDSS ~ G0*Vp0/3 = {IDSS*1e3:.1f} mA")
for VGS in (0, -1, -2, -3):
    ID = IDSS * (1 - VGS / Vp) ** 2 if VGS > Vp else 0
    gm = 2 * IDSS / abs(Vp) * (1 - VGS / Vp) if VGS > Vp else 0
    print(f"VGS = {VGS:2d} V: ID = {ID*1e3:6.2f} mA, gm = {gm*1e3:.2f} mS")
# internal pinch-off 7.73 V -> VGS(off) = Vbi - Vp0 = -6.93 V
# open-channel conductance G0 = 35.24 mS (R0 = 28 ohm)
# IDSS ~ G0*Vp0/3 = 90.8 mA
# VGS =  0 V: ID =  90.84 mA, gm = 26.21 mS
# VGS = -1 V: ID =  66.52 mA, gm = 22.43 mS
# VGS = -2 V: ID =  45.98 mA, gm = 18.65 mS
# VGS = -3 V: ID =  29.23 mA, gm = 14.87 mS

A 1 µm half-thickness channel doped 10¹⁶ gives an internal pinch-off of 7.7 V and a gate cut-off near −6.9 V. A 1 mm-wide, 10 µm-long channel conducts 35 mS when open, giving I_DSS ≈ 91 mA — a power-class JFET. Small-signal JFETs use thinner, narrower channels (I_DSS of a few mA, V_P of −0.5 to −4 V).

Common mistakes

Applications

Key takeaways

Going further