Frequency-Domain Methods & Analog PID Control

Analog electronics as a control system. Learn Laplace transforms and transfer functions for circuits, poles and zeros in the s-plane, step response vs pole location (first- and second-order), steady-state error and system type, loop shaping with Bode plots, P, PI, PD and PID controllers built with op-amps (component formulas), integrator wind-up and output saturation, lead/lag compensators, and practical analog loops (temperature, motor speed, LED current, power-supply error amplifiers) — with Python simulating an op-amp PI controller on a first-order plant, including rail saturation.

Many analog circuits are control loops: regulators hold a voltage, motor drivers hold a speed, heaters hold a temperature. The same frequency-domain tools used for amplifier stability let you design controllers that are fast, accurate and stable.

Op-amps implement proportional, integral and derivative actions directly with resistors and capacitors — continuous-time controllers with no sampling delay.

An analogy

A PID controller is like driving to keep a set speed: P reacts to how far off you are now, I remembers how long you've been off (to remove persistent error on hills), and D reacts to how fast the error is changing (to avoid overshooting when the speed starts rising).

Transfer functions and poles

Replace capacitors with 1/(sC) and inductors with sL to write any linear circuit as a ratio of polynomials in s. Pole locations determine the natural response: real negative poles decay exponentially; complex pairs oscillate while decaying (ζ < 1); poles in the right half-plane grow (unstable). Zeros shape the response and can cause overshoot or undershoot.

P, I and D actions

What each term does:

Loop shaping

Design the open-loop Bode plot: high gain at low frequency (accuracy), crossover at the desired bandwidth with ≥ 45–60° phase margin, and falling gain beyond (noise immunity). Place the PI zero a factor 3–10 below crossover, and lead compensation around crossover. Power-supply error amplifiers use the same ideas as Type II/III compensators.

Practical issues

Actuators and op-amps saturate: during long errors the integrator winds up and causes large overshoot — add anti-windup (clamp diodes/zeners across the integrator capacitor, or conditional integration). Sensor noise and delays limit bandwidth. Thermal plants have long delays — use conservative tuning (Ziegler–Nichols or IMC rules as starting points). Verify with step tests at several operating points.

Formulas

Worked example: PI values

Given: R₁ 10 kΩ, R₂ 100 kΩ, C 0.1 µF

Find: K_p and T_i.

Answer: K_p = 10, T_i = 10 ms

Worked example: Steady-state error (P only)

Given: Loop DC gain 9

Find: e_ss for a step.

Answer: 10%

Worked example: Settling time

Given: ζ 0.5, ω_n 100 rad/s

Find: t_s (2%).

Answer: 80 ms

Op-amp PID controller

  Error e = setpoint − measurement (difference amp)
            ┌── R₂ ──||C_I──┐   (PI: gain R₂/R₁, integral zero 1/(2πR₂C_I))
  e ── R₁ ──┤−              │
     C_D ∥  │  ▷────────────┴── u → driver → plant
            ┤+ (GND)
  C_D across R₁ adds derivative action (limit with a series resistor)

An inverting amplifier with a series R–C in its feedback path gives proportional plus integral action; a capacitor across the input resistor adds derivative action (with a small series resistor to limit high-frequency gain). A second inverting stage restores the sign.

Simulating an op-amp PI loop

import math
# Analog PI(D) controller on a first-order plant: component values and a simulated step response
R1, R2, C = 10e3, 47e3, 1e-6                     # PI: Kp = R2/R1, Ti = R2*C
Kp, Ti = R2 / R1, R2 * C
print(f"op-amp PI: Kp = {Kp:.1f}, Ti = {Ti*1e3:.0f} ms (integral zero at {1/(2*math.pi*Ti):.1f} Hz)")
K_plant, tau = 2.0, 0.1                          # plant: 2 / (0.1 s + 1)
dt, y, integ, ref = 1e-4, 0.0, 0.0, 1.0
peak, t_settle = 0.0, None
for n in range(int(1.0 / dt)):
    e = ref - y
    integ += e * dt
    u = Kp * (e + integ / Ti)
    u = max(-12.0, min(12.0, u))                  # op-amp output saturates at the rails
    y += dt * (K_plant * u - y) / tau
    peak = max(peak, y)
    if abs(y - ref) > 0.02:
        t_settle = None
    elif t_settle is None:
        t_settle = n * dt
print(f"step: overshoot {(peak-1)*100:.1f}%, 2% settling at {t_settle*1e3:.0f} ms, final error {abs(ref-y)*100:.3f}% of setpoint")
# op-amp PI: Kp = 4.7, Ti = 47 ms (integral zero at 3.4 Hz)
# step: overshoot 5.6%, 2% settling at 104 ms, final error 0.000% of setpoint

With K_p = 4.7 and T_i = 47 ms on a plant of gain 2 and time constant 100 ms, the loop reaches the setpoint with ~6% overshoot and settles within 2% in about 0.1 s; the integrator removes steady-state error completely. The simulation clamps the controller output at the ±12 V rails, as a real op-amp would.

Common mistakes

Applications

Key takeaways

Going further