Switching Regulators: Buck, Boost & Buck-Boost

Efficient DC–DC conversion. Learn why switching beats linear, the buck, boost, buck-boost/inverting and SEPIC topologies with their volt-second balance and duty-cycle equations, inductor selection (ripple current, saturation, DCR), output and input capacitor selection (ripple, ESR, RMS current), CCM vs DCM, synchronous rectification, loss mechanisms and efficiency, voltage- and current-mode control and loop compensation basics, switching noise and layout (hot loops) — with Python designing a 12 V → 3.3 V buck and estimating ripple and efficiency.

A switching regulator chops the input with a transistor and smooths the pulses with an inductor and capacitor. Ideal switches and reactive components dissipate no power, so efficiencies of 85–97% are routine, even with large voltage ratios.

The price is ripple, electromagnetic interference and a feedback loop that must be compensated — which is why analog engineers must understand switchers even if they buy them as modules.

An analogy

A buck converter is like filling a glass from a fire hose by opening the tap briefly and often: the inductor is a flywheel that keeps the flow smooth between bursts, and the capacitor is the glass that averages the level.

Topologies

Choose by voltage relationship:

Component selection

Inductor: value for 20–40% ripple, saturation current above peak (I_out + ΔI_L/2 plus margin), low DCR, shielded for EMI. Output capacitor: ceramics for low ESR (derate for DC bias), set by ripple and load-transient requirements. Input capacitor: handles RMS current ≈ I_out·√(D(1 − D)) — place it at the switches. Switches: R_DS(on) vs gate charge trade-off; synchronous rectification replaces the diode for efficiency at low output voltages.

Losses and efficiency

Conduction (I²R in switches, inductor DCR, capacitor ESR), switching (V·I overlap during transitions, C_oss charging, reverse recovery), gate drive (Q_g·V·f), core losses, and controller quiescent current. Higher f_sw means smaller L and C but more switching loss. Light-load efficiency uses pulse-skipping/PFM modes at the expense of variable-frequency ripple.

Control, stability and EMI

Voltage-mode control has a double LC pole requiring Type III compensation; peak current-mode control makes the inductor a current source (single pole, Type II compensation) with inherent cycle-by-cycle current limiting but needs slope compensation above D = 50%. Boost and buck-boost have a right-half-plane zero limiting bandwidth. EMI: minimise the hot-loop area, keep the SW node copper small, use a solid ground plane, input π-filters, spread-spectrum and snubbers; follow CISPR 25/32 limits for products.

Formulas

Worked example: Buck duty

Given: 12 V → 5 V

Find: D.

Answer: 0.417

Worked example: Ripple current

Given: 12 → 5 V, L 10 µH, 300 kHz

Find: ΔI_L.

Answer: ≈ 0.97 A pp

Worked example: Boost duty

Given: 5 V → 12 V

Find: D.

Answer: 0.583

Synchronous buck converter

  V_in 12 V ──┬── C_in ── GND
              Q_high (PWM, D)
              ├── SW node ── L 4.7 µH ──┬── V_out 3.3 V / 2 A
              Q_low (1 − D)             C_out 22 µF ── R_FB divider → controller
              GND                        GND
  Hot loop: C_in → Q_high → Q_low → C_in  (keep tiny!)

The high-side switch connects the inductor to the input for time DT; then the low-side switch (or a diode) provides a freewheeling path. The inductor current ramps up and down around the load current; the output capacitor absorbs the ripple. The input-capacitor/switch loop carries sharp current edges and must be physically minimal.

Buck design: ripple and efficiency

import math
# Buck converter: duty, inductor ripple, output ripple, efficiency; boost duty for comparison
Vin, Vout, Iout, fsw = 12.0, 3.3, 2.0, 500e3
D = Vout / Vin
L = 4.7e-6
dI = (Vin - Vout) * D / (fsw * L)
print(f"buck duty {D:.3f}; inductor ripple {dI:.2f} A pp ({dI/Iout*100:.0f}% of Iout); peak current {Iout+dI/2:.2f} A")
Cout, ESR = 22e-6, 5e-3
dV_cap = dI / (8 * fsw * Cout)
dV_esr = dI * ESR
print(f"output ripple: capacitive {dV_cap*1e3:.1f} mV + ESR {dV_esr*1e3:.1f} mV")
Rds_hi, Rds_lo, tsw, DCR = 30e-3, 15e-3, 10e-9, 20e-3   # tsw = (tr + tf)/2; gate-drive and core losses ignored
Pc = Iout**2 * (Rds_hi * D + Rds_lo * (1 - D)) + Iout**2 * DCR
Ps = Vin * Iout * tsw * fsw
Po = Vout * Iout
print(f"losses: conduction {Pc*1e3:.0f} mW, switching {Ps*1e3:.0f} mW -> efficiency {Po/(Po+Pc+Ps)*100:.1f}%")
# Boost 3.7 V -> 5 V
print(f"boost 3.7 V -> 5 V: D = {1 - 3.7/5:.2f}; input current for 1 A out at 90% eff: {5*1/(0.9*3.7):.2f} A")
print(f"CCM/DCM boundary for this buck: Iout < {dI/2:.2f} A enters DCM")
# buck duty 0.275; inductor ripple 1.02 A pp (51% of Iout); peak current 2.51 A
# output ripple: capacitive 11.6 mV + ESR 5.1 mV
# losses: conduction 156 mW, switching 120 mW -> efficiency 96.0%
# boost 3.7 V -> 5 V: D = 0.26; input current for 1 A out at 90% eff: 1.50 A
# CCM/DCM boundary for this buck: Iout < 0.51 A enters DCM

At 500 kHz a 4.7 µH inductor gives about 1 A of ripple (51% of 2 A — on the high side; 6.8–10 µH would bring it to 25–35%). Output ripple is ~17 mV with 22 µF ceramics. Conduction and switching losses of ~0.28 W give ~96% (real converters land at 88–93% once gate drive, core and controller losses are added). Below 0.51 A load the inductor current would reach zero — the converter enters DCM unless it is forced-PWM synchronous.

Common mistakes

Applications

Key takeaways

Going further