FPGA Design

FPGAs are reconfigurable chips made of logic blocks, memories and DSP slices connected by programmable routing. Learn LUTs and flip-flops, CLBs, block RAM, DSP slices, clocking (PLLs/MMCMs), the FPGA flow (synthesis, implementation, bitstream), timing constraints, resource estimation, and SoC FPGAs.

FPGAs let you build custom hardware without fabricating a chip — used for prototyping ASICs, low-volume products, networking, radar, video processing and AI acceleration. Designs can be updated in the field.

An analogy

An FPGA is like a huge LEGO board: the bricks (LUTs, flip-flops, RAM, DSP) are fixed, but you can connect them in any pattern and rebuild whenever you like.

Architecture

Configurable logic blocks contain 6-input LUTs (any 6-input function), flip-flops and carry chains. Block RAMs (18/36 Kb), DSP slices (e.g. 27 × 18 multipliers), clock managers (PLL/MMCM), I/O banks with SerDes transceivers.

Design flow

RTL → synthesis (map to LUTs/FFs) → implementation (place and route) → timing analysis → bitstream → program via JTAG or flash. Vivado (AMD/Xilinx), Quartus (Intel/Altera), Libero (Microchip), open-source Yosys/nextpnr.

Timing closure

Critical paths are LUT levels plus routing delay. Pipelining, register duplication, floorplanning and proper constraints raise f_max. Check WNS ≥ 0 and no hold violations.

SoC FPGAs and HLS

Zynq and Agilex SoCs combine ARM cores with FPGA fabric. High-level synthesis (Vitis HLS) converts C++ to RTL. Partial reconfiguration swaps functions at runtime. Power, security (bitstream encryption) and radiation (space) are advanced concerns.

Formulas

• LUT capacity: k-input LUT stores 2^k bits (any k-input function)
• Path delay: t = t_cq + Σ(LUT delay + routing) + t_su
• BRAMs needed: N = ⌈depth/blk_depth⌉ × ⌈width/blk_width⌉

Worked example: Path delay

Given: t_cq 0.3 ns, 3 LUT levels × (0.4 ns LUT + 0.5 ns routing), t_su 0.1 ns

Find: f_max.

• t = 0.3 + 3 × 0.9 + 0.1 = 3.1 ns
• f_max = 323 MHz

Answer: ≈ 323 MHz

Worked example: Block RAM count

Given: Buffer 32 768 × 32 bits; BRAM36 configured 1K × 36

Find: BRAMs.

• ⌈32 768/1024⌉ × ⌈32/36⌉ = 32 × 1

Answer: 32 BRAM36 blocks (1 Mbit)

Timing constraints (XDC/SDC) for an FPGA design

# 100 MHz board oscillator
create_clock -name sys_clk -period 10.000 [get_ports clk_100m]

# Generated 200 MHz clock from the MMCM is derived automatically in Vivado.
# Inputs arrive 2 ns after the clock edge from an external ADC
set_input_delay  -clock sys_clk 2.0 [get_ports {adc_data[*]}]
set_output_delay -clock sys_clk 1.5 [get_ports {dac_data[*]}]

# Asynchronous reset button: do not time it
set_false_path -from [get_ports btn_rst]

# Pin assignments
set_property PACKAGE_PIN W5  [get_ports clk_100m]
set_property IOSTANDARD LVCMOS33 [get_ports clk_100m]

Constraints tell the tools the clock frequency and I/O timing so implementation optimises the right paths. Without them, a design may pass simulation yet fail on hardware.

Common mistakes

• Wrong: No timing constraints. — Right: Always constrain clocks and I/O.
• Wrong: Gated or logic-generated clocks. — Right: Use clock enables and dedicated clock resources.

Applications

• ASIC prototyping: Emulate chips before tape-out.
• Video & radar processing: Parallel DSP pipelines.
• Networking & HFT: Low-latency packet processing.

Key takeaways

• LUTs + FFs + BRAM + DSP + routing.
• RTL → synth → P&R → bitstream.
• Constrain and close timing.
• SoC FPGAs combine CPUs and fabric.

Going further

• Partial reconfiguration: Swap regions at runtime.
• HLS: C++ to hardware.
• High-speed transceivers: PCIe, 100G Ethernet on FPGAs.