RTL Design & HDLs

Verilog, SystemVerilog, CDC and FPGAs. Describing hardware in code: Verilog RTL coding, SystemVerilog, clock-domain crossing and metastability, and FPGA prototyping.

• RTL Design with Verilog — Register-transfer level design describes hardware as registers and the logic between them. Learn Verilog modules, ports, wires and regs, continuous vs procedural assignments, blocking vs non-blocking, combinational and sequential always blocks, finite state machines, parameters, testbenches, and synthesisable coding rules.
• SystemVerilog & Verification — Verification takes more than half of chip-design effort. Learn SystemVerilog design enhancements (logic, always_ff/always_comb, interfaces, structs), verification features (classes, constrained-random stimulus, functional coverage, assertions/SVA), UVM testbench architecture, and formal verification basics.
• Clock-Domain Crossing & Metastability — Modern SoCs have dozens of unrelated clocks. Learn what metastability is, why it cannot be eliminated, the MTBF equation, two-flop synchronizers, pulse and handshake synchronizers, Gray-coded asynchronous FIFOs, reset synchronizers, reconvergence problems and how CDC checking tools find bugs that simulation misses.
• FPGA Design — FPGAs are reconfigurable chips made of logic blocks, memories and DSP slices connected by programmable routing. Learn LUTs and flip-flops, CLBs, block RAM, DSP slices, clocking (PLLs/MMCMs), the FPGA flow (synthesis, implementation, bitstream), timing constraints, resource estimation, and SoC FPGAs.