VHDL-2019 Features

Tool support is growing (NVC, Aldec, partial GHDL/Questa):

Interfaces & mode views: group record fields with directions — bus interfaces as a single port:

Conditional analysis (` if TOOL_VENDOR = "..." then ` ... end if ``).

64-bit integer range, std.env additions (date/time, directory access), garbage collection of access types, function knows return type (return type inference), generics on subprograms improvements, file and protected type enhancements, sequential block statements, empty records, standard API for interfaces to C (VHPI improvements), shorter syntax forms (optional is keywords, trailing semicolons in interface lists).

type axis_t is record
  tdata  : std_logic_vector(31 downto 0);
  tvalid : std_logic;
  tready : std_logic;
end record;

view axis_master of axis_t is
  tdata, tvalid : out;
  tready        : in;
end view;
alias axis_slave is axis_master'converse;

entity producer is
  port (clk : in std_logic; m_axis : view axis_master);
end entity;