VHDL-2008 Features

VHDL-2008 is supported by GHDL, NVC, Questa, Vivado (synthesis & sim), Quartus Pro, and others.

VHDL-2008 is supported by GHDL, NVC, Questa, Vivado (synthesis & sim), Quartus Pro, and others. Enable it (--std=08, file type "VHDL 2008").

automatic sensitivity list Read out ports cnt_out <= cnt_out + 1; (no internal copy needed)

Conditional/selected assignments in processes y <= a when s = '1' else b; inside a process

if... generate with elsif/else, case... generate Condition operator ?? / implicit

if en then (std_logic used as boolean) Matching operators & case?, select? if a ?= "1-0" then Unary reduction operators or v, and v, xor v Sized/signed bit-string literals 8x"A", 12sx"F", 5d"17" Unconstrained element types

type arr is array (natural range <>) of std_logic_vector; Generic types, packages & subprograms

generic (type T; function "<"(a, b: T) return boolean) fixed_pkg, float_pkg synthesizable fixed/floating point arithmetic on std_logic_vector to_string, to_hstring, to_ostring report to_hstring(data); std.env.stop / finish end simulation cleanly

External names (hierarchical references) << signal.tb.dut.internal_sig: std_logic >> force / release dut_sig <= force '1'; (testbench) context work.ctx;

Keyword all in sensitivity, minimum/maximum functions maximum(a, b) Expressions in port maps port map (d => a and b) -- psl assert always... or native

-- External names: peek into the DUT from the testbench without adding ports
alias dut_state is << signal .counter_tb.dut.state : state_t >>;
assert dut_state /= ERROR report "DUT entered ERROR state";

-- Generic subprogram/type
entity sorter is
  generic (type elem_t; function "<"(l, r : elem_t) return boolean is <>);
  ...