Operators

Precedence (high → low): ** abs not → * / mod rem → unary + - → + - & → shifts → relational → logical (and or ...

and or nand nor xor xnor not on bit, boolean, std_logic, vectors (element-wise) Matching relational (2008) result std_ulogic, '-' matches anything sll srl sla sra rol ror prefer shift_left/shift_right (numeric_std) + - and & (concatenation)

/, mod, rem only for powers of 2 in synthesis (or integers) ** mostly for constants Condition (2008) converts std_ulogic to boolean Reduction (2008) unary and or xor nand nor xnor or vec = any bit set

Precedence (high → low): ** abs not → * / mod rem → unary + - → + - & → shifts → relational → logical (and or ... have equal precedence: use parentheses when mixing).

y <= (a and b) or c;                      -- parentheses required when mixing and/or
bus16 <= hi_byte & lo_byte;               -- concatenation
shifted <= shift_left(u, 2);              -- numeric_std shift
rotated <= rotate_right(u, 1);
any_set <= or data;                       -- VHDL-2008 reduction
parity <= xor data;
sum9 <= ('0' & a) + ('0' & b);            -- extend to keep the carry
sum9 <= resize(a, 9) + resize(b, 9);
prod <= a * b;                            -- result width = a'length + b'length