Objects: Signals, Variables, Constants, Files

architecture, package, entity ports <=, scheduled (takes effect after a delta/time) wires, registers process, subprogram :=, immediately shared variable

:=, must be of protected type (VHDL-2002+) testbench shared state via file operations text/binary files

architecture rtl of example is
  constant WIDTH : natural := 8;
  signal   acc   : unsigned(WIDTH-1 downto 0) := (others => '0');   -- initial value (sim; also FPGA power-up)
begin
  process (clk)
    variable tmp : unsigned(WIDTH-1 downto 0);
  begin
    if rising_edge(clk) then
      tmp := acc + 1;          -- immediate
      acc <= tmp;              -- scheduled for the end of the process
    end if;
  end process;
end architecture;

6.1 Aliases

alias opcode : std_logic_vector(3 downto 0) is instr(31 downto 28);
alias sign_bit : std_logic is value(value'high);