MOSFET Device Physics & Models

The MOSFET is the building block of every digital and analog chip. Learn the MOS capacitor, inversion and threshold voltage, the cut-off/triode/saturation regions, the square-law I–V equations, channel-length modulation, body effect, subthreshold conduction, velocity saturation and short-channel effects, and why FinFETs and nanosheets replaced planar transistors.

A MOSFET is a voltage-controlled switch and amplifier. The gate, separated from the silicon by a thin oxide, attracts carriers to the surface and forms a conducting channel between source and drain. No gate current flows (ideally), which is why billions of MOSFETs can switch with little static power.

Circuit designers use compact equations (square law, then BSIM models) to predict current. Understanding where those equations come from — and where they break down in nanometre transistors — is essential for both digital timing and analog design.

An analogy

A MOSFET is a water tap. The gate voltage is how far you open the valve (it doesn't let water in itself); the drain–source voltage is the water pressure. Below the threshold the tap is shut; slightly open, flow grows with pressure (triode); fully open, the pipe itself limits flow (saturation).

Structure and operation

An NMOS has n⁺ source and drain in a p-type body, with a gate on top of a thin oxide. A positive gate voltage repels holes and attracts electrons to the surface; above V_t an inversion layer (channel) of electrons connects source and drain. PMOS is the mirror image with holes, used for pull-up networks in CMOS.

Three regions of operation

Which equation applies depends on V_GS and V_DS:

Second-order effects

Channel-length modulation: in saturation the pinch-off point moves, so I_D rises slightly with V_DS (finite r_o, limited analog gain). Body effect: a source above the body raises V_t (stacked transistors in NAND gates get weaker). Subthreshold conduction: below V_t current falls only exponentially — the leakage that dominates idle power in modern chips.

Short channels and new device architectures

In short channels, carriers hit velocity saturation (I_D ∝ V_ov, not V_ov²), the drain lowers the source barrier (DIBL, V_t drops with V_DS), and the gate loses control of the channel. FinFETs wrap the gate around a thin fin on three sides; gate-all-around nanosheets surround it completely, restoring electrostatic control and keeping subthreshold slope near the 60 mV/decade room-temperature limit.

Formulas

Worked example: Saturation current

Given: k′ = 690 µA/V², W/L = 10; V_ov = 0.3 V, λ ignored

Find: I_D.

Answer: I_D ≈ 311 µA

Worked example: Transconductance

Given: I_D = 311 µA, V_ov = 0.3 V

Find: g_m.

Answer: g_m ≈ 2.07 mA/V

Worked example: Body effect

Given: V_t0 = 0.35 V, γ = 0.4 √V, 2φ_F = 0.8 V, V_SB = 0.5 V

Find: V_t.

Answer: ΔV_t ≈ 0.098 V → V_t ≈ 0.45 V

Square-law I–V model of an NMOS transistor

eps_ox, tox = 3.9 * 8.854e-14, 2e-7             # F/cm, 2 nm oxide
Cox = eps_ox / tox                               # F/cm^2
k = 400 * Cox                                    # mu_n * Cox, A/V^2
W_L, Vt, lam = 10, 0.35, 0.1

def drain_current(vgs, vds):
    vov = vgs - Vt
    if vov <= 0:
        return 0.0                               # (ignoring subthreshold)
    if vds < vov:                                # triode
        return k * W_L * (vov * vds - vds**2 / 2)
    return 0.5 * k * W_L * vov**2 * (1 + lam * vds)   # saturation

print(f"Cox = {Cox*1e15/1e8:.2f} fF/um^2, k' = {k*1e6:.0f} uA/V^2")
for vds in (0.1, 0.3, 0.6, 1.0):
    print(f"VGS=0.65 V, VDS={vds:.1f} V -> ID = {drain_current(0.65, vds)*1e6:6.1f} uA")
# Cox = 17.27 fF/um^2, k' = 691 uA/V^2
# VGS=0.65 V, VDS=0.1 V -> ID =  172.7 uA
# VGS=0.65 V, VDS=0.3 V -> ID =  310.8 uA
# VGS=0.65 V, VDS=0.6 V -> ID =  329.4 uA
# VGS=0.65 V, VDS=1.0 V -> ID =  341.9 uA

Current rises quickly while V_DS < V_ov (triode) and then flattens (saturation); the small remaining slope is channel-length modulation λ. Real sub-100 nm devices need BSIM models, but this model captures the regions and trends.

SPICE netlist to sweep an NMOS

* NMOS output characteristics
.include models.lib           ; process model card (BSIM4)
M1  d g 0 0  nmos  W=1u L=100n
VGS g 0 DC 0.65
VDS d 0 DC 0
.dc VDS 0 1.0 0.01 VGS 0.4 1.0 0.2   ; nested sweep
.print dc I(VDS)
.end

SPICE solves the real device model at every bias point. Nested .dc sweeps produce the family of I_D–V_DS curves you see in datasheets and textbooks.

Common mistakes

Applications

Key takeaways

Going further