Logic Gates

Logic gates are the atoms of digital electronics. Learn binary signals and logic levels, the basic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) with truth tables and symbols, universal gates, CMOS implementation, noise margins, fan-out, propagation delay and dynamic power.

Digital circuits represent information with two voltage levels — LOW (0) and HIGH (1). Gates combine these according to Boolean rules. Billions of gates, built from CMOS transistors, make up every processor and memory chip.

An analogy

Gates are like simple decision rules: AND = 'only if both switches are on', OR = 'if either switch is on', NOT = 'the opposite'.

Truth tables

A truth table lists the output for every input combination (2ⁿ rows). AND is 1 only when all inputs are 1; OR is 1 when any input is 1; XOR is 1 when inputs differ; NAND/NOR are inverted AND/OR.

Universal gates and CMOS

Any logic function can be built from NAND alone (or NOR alone). In CMOS, a NAND is two PMOS in parallel (pull-up) and two NMOS in series (pull-down) — naturally inverting gates are the cheapest.

Electrical characteristics

Logic families (TTL, LVTTL, LVCMOS 3.3/1.8 V) define voltage thresholds. Noise margins tell how much noise a signal can tolerate. Fan-out is how many inputs one output can drive; t_pd is the delay from input change to output change.

Power

CMOS draws power mainly when switching: P = αCV²f, plus leakage in modern nanometre processes. Lowering V_DD is the most effective way to cut power (quadratic).

Formulas

• Basic gates: AND Y = A·B, OR Y = A + B, NOT Y = A′, XOR Y = A ⊕ B = A′B + AB′
• Universal gates: NAND Y = (A·B)′, NOR Y = (A + B)′
• Noise margins: NM_H = V_OH − V_IH, NM_L = V_IL − V_OL
• CMOS dynamic power: P = α C V_DD² f

Worked example: Noise margins (LVTTL)

Given: V_OH 2.4 V, V_IH 2.0 V, V_IL 0.8 V, V_OL 0.4 V

Find: NM_H, NM_L.

• NM_H = 2.4 − 2.0 = 0.4 V
• NM_L = 0.8 − 0.4 = 0.4 V

Answer: 0.4 V each

Worked example: Dynamic power

Given: C = 10 pF, V_DD = 3.3 V, f = 10 MHz, α = 0.5

Find: P.

• P = 0.5 × 10 × 10⁻¹² × 3.3² × 10⁷ = 0.545 mW

Answer: ≈ 0.54 mW

Gates in Verilog

module gates (
  input  wire a, b,
  output wire y_and, y_or, y_not, y_nand, y_nor, y_xor, y_xnor
);
  assign y_and  = a & b;
  assign y_or   = a | b;
  assign y_not  = ~a;
  assign y_nand = ~(a & b);
  assign y_nor  = ~(a | b);
  assign y_xor  = a ^ b;
  assign y_xnor = ~(a ^ b);
endmodule

Hardware description languages describe gates with bitwise operators. Synthesis tools turn these into real gates or FPGA look-up tables.

Common mistakes

• Wrong: Mixing 5 V and 3.3 V logic directly. — Right: Check thresholds and use level shifters.
• Wrong: Leaving CMOS inputs floating. — Right: Tie unused inputs to a defined level.

Applications

• Glue logic: Combining enable signals and chip selects.
• Processors: Billions of gates in ALUs and control.
• Safety interlocks: Hard-wired AND/OR conditions.

Key takeaways

• AND, OR, NOT, NAND, NOR, XOR, XNOR.
• NAND/NOR are universal.
• Check noise margins and fan-out.
• P = αCV²f.

Going further

• Transmission gates: CMOS pass-gate logic.
• Leakage power: Subthreshold currents in advanced nodes.
• Schmitt triggers: Hysteresis for noisy inputs.