Complete FPGA Projects
34.1 LED blinker (the FPGA "Hello World")
Constraints (e.g., Basys 3):
Open-source flow for a Lattice iCE40 board:
library ieee;
use ieee.std_logic_1164.all;
entity blinky is
generic (CLK_FREQ : positive := 100_000_000);
port (
clk : in std_logic;
led : out std_logic);
end entity;
architecture rtl of blinky is
signal cnt : integer range 0 to CLK_FREQ / 2 - 1 := 0;
signal state : std_logic := '0';
begin
process (clk)
begin
if rising_edge(clk) then
if cnt = CLK_FREQ / 2 - 1 then
cnt <= 0;
state <= not state; -- toggle every 0.5 s → 1 Hz blink
else
cnt <= cnt + 1;
end if;
end if;
end process;
led <= state;
end architecture;set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports led]
create_clock -period 10.000 -name sys_clk [get_ports clk]yosys -m ghdl -p 'ghdl --std=08 blinky.vhd -e blinky; synth_ice40 -json blinky.json'
nextpnr-ice40 --up5k --package sg48 --json blinky.json --pcf board.pcf --asc blinky.asc
icepack blinky.asc blinky.bin && iceprog blinky.bin34.2 Multiplexed 4-digit seven-segment counter
Combine: a 1 kHz refresh tick, a 2-bit digit selector, a BCD counter incremented at 1 Hz, the seven-segment decoder (§12.6), and active-low anode drivers. Teaches clock enables, hierarchy, and time-multiplexing.
34.3 Stopwatch / digital clock
Buttons (debounced, edge-detected) for start/stop/reset/lap; cascaded BCD counters for minutes:seconds:hundredths; FSM for modes.
34.4 UART echo & command processor
UART RX → FIFO → command parser FSM → register writes / LED control → UART TX responses. Test from a PC terminal (PuTTY, screen, Python pyserial).
34.5 VGA pattern generator & Pong
VGA timing generator (§28.4), color bars, moving sprites, collision detection, score display with a character ROM — a classic complete project combining counters, FSMs, ROMs, and arithmetic.
34.6 PWM, audio & sensors
PWM LED dimming and servo control, sigma-delta DAC for audio tones, SPI ADC readout, I2C temperature sensor display.