On-Chip Buses

Signals: tdata, tvalid, tready, optional tlast, tkeep, tuser, tid, tdest.

29.1 AXI4-Stream (unidirectional data streams)

Signals: tdata, tvalid, tready, optional tlast, tkeep, tuser, tid, tdest. A transfer occurs when tvalid and tready are both '1' on a rising clock edge. Rules: a source must not wait for tready before asserting tvalid; once asserted, tvalid and data must stay stable until accepted.

Full-throughput pipelines with registered tready need a skid buffer.

-- Pass-through register stage (skid buffer omitted for simplicity)
process (clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      m_tvalid <= '0';
    elsif m_tready = '1' or m_tvalid = '0' then        -- output empty or being consumed
      m_tvalid <= s_tvalid;
      m_tdata  <= std_logic_vector(unsigned(s_tdata) + 1);   -- processing: add 1
      m_tlast  <= s_tlast;
    end if;
  end if;
end process;
s_tready <= m_tready or not m_tvalid;

29.2 AXI4 & AXI4-Lite (memory-mapped)

Five channels: AW (write address), W (write data), B (write response), AR (read address), R (read data), each with valid/ready handshakes. AXI4-Lite: single transfers, 32/64-bit, used for control/status registers. AXI4 (full): bursts, IDs, out-of-order — used for memory access (DMA). Typical design: an AXI4-Lite slave register bank exposing control registers to a processor (Zynq PS, MicroBlaze, Nios V, RISC-V soft cores).

29.3 Other buses

Avalon-MM / Avalon-ST (Intel).

Wishbone (open-source, OpenCores).

APB / AHB (Arm AMBA, simpler peripherals).

TileLink (RISC-V ecosystem).

29.4 Register bank generation

Tools generate VHDL register maps from descriptions: hdl_registers, Cheby, RgGen, PeakRDL (SystemRDL), airhdl, Vivado/Quartus IP templates.