FPGA Architecture & Resources

Major families: AMD/Xilinx (Spartan, Artix, Kintex, Virtex, Zynq, Versal), Intel/Altera (Cyclone, Arria, Stratix, Agilex), Lattice (iCE40, ECP5, CrossLink, Certus), Microchip (PolarFire, IGLOO), Gowin, Efinix.

25.1 Building blocks

LUT (look-up table) 4–6 input truth table implementing any logic function; can act as small RAM/shift register registers in each logic cell/slice Carry chains fast dedicated adders/comparators Block RAM (BRAM)

18/36 Kb dual-port memories (UltraRAM 288 Kb in UltraScale+) DSP slices hardened multiply-accumulate units (e.g., DSP48E2: 27×18 MAC) Clock resources global clock buffers (BUFG), regional clocks, PLLs/MMCMs for frequency synthesis I/O blocks configurable voltage standards, SERDES, DDR, delay lines (IDELAY) multi-gigabit serial links (PCIe, Ethernet, JESD204)

PCIe controllers, Ethernet MACs, DDR memory controllers, ARM processors (Zynq, Agilex SoC, PolarFire SoC)

25.2 Instantiating primitives

Prefer vendor IP wizards (Clocking Wizard, PLL IP) or inference for portability; use XPM macros (Xilinx Parameterized Macros) for CDC, FIFOs, and RAMs.

library unisim;
use unisim.vcomponents.all;

u_bufg : BUFG port map (I => clk_raw, O => clk_buf);

u_mmcm : MMCME2_BASE
  generic map (CLKIN1_PERIOD => 10.0, CLKFBOUT_MULT_F => 10.0, CLKOUT0_DIVIDE_F => 8.0)
  port map (CLKIN1 => clk_100, CLKOUT0 => clk_125, CLKFBIN => fb, CLKFBOUT => fb,
            LOCKED => locked, RST => '0', PWRDWN => '0', ...);

25.3 Physical constraints

Pin locations and I/O standards in constraint files:

Quartus uses .qsf (set_location_assignment PIN_AF14 -to clk), Lattice .lpf/.pdc, nextpnr .pcf.

# Vivado XDC
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]

25.4 On-chip debugging

Vivado ILA (Integrated Logic Analyzer), VIO (virtual I/O) — mark signals with mark_debug.

Intel Signal Tap, Lattice Reveal, open-source LiteScope.

Capture internal signals in hardware at speed, triggered by conditions.