Processes & Sequential Statements

A process is a concurrent statement containing sequential statements.

10.1 The process statement

A process is a concurrent statement containing sequential statements. It runs once at time 0, then re-runs whenever a signal in its sensitivity list changes (or suspends at wait statements).

A process has either a sensitivity list or wait statements, never both.

mux_proc : process (a, b, sel)          -- sensitivity list
begin
  if sel = '1' then
    y <= b;
  else
    y <= a;
  end if;
end process mux_proc;

comb : process (all)                    -- VHDL-2008: automatically sensitive to all read signals
begin
  ...
end process;

10.2 if / elsif / else

if reset = '1' then
  count <= (others => '0');
elsif enable = '1' then
  count <= count + 1;
else
  null;                                  -- explicit "do nothing"
end if;

10.3 case

case? (VHDL-2008) supports don't-care matching: when "1--" => ....

case sel is
  when "00"   => y <= a;
  when "01"   => y <= b;
  when "10" | "11" => y <= c;            -- multiple choices
  when others => y <= 'X';               -- must cover all values
end case;

case to_integer(addr) is
  when 0 to 15  => region <= RAM;         -- ranges for integer/enum
  when 16 to 31 => region <= IO;
  when others   => region <= NONE;
end case;

10.4 Loops

In synthesis, for loops are unrolled into parallel hardware (bounds must be static).

for i in 0 to 7 loop                     -- loop index is implicitly declared, read-only
  parity_v := parity_v xor data(i);
end loop;

for i in data'range loop ... end loop;

while count_v < 10 loop                  -- while loops: mostly simulation
  count_v := count_v + 1;
end loop;

outer : for i in 0 to 3 loop
  inner : for j in 0 to 3 loop
    next inner when i = j;               -- skip iteration
    exit outer when matrix(i, j) = 0;    -- leave loop
  end loop inner;
end loop outer;

loop                                     -- infinite loop (testbenches)
  wait until rising_edge(clk);
  exit when done = '1';
end loop;

10.5 wait statements (simulation / testbenches)

Synthesis tools only accept limited forms (e.g., a single wait until rising_edge(clk); at the top of a process).

wait;                                    -- suspend forever
wait for 10 ns;                          -- wait a time
wait until rising_edge(clk);             -- wait for a condition
wait until done = '1' for 1 ms;          -- condition with timeout
wait on a, b;                            -- wait for any change of a or b

10.6 Other sequential statements

null;
report "message" severity note;          -- note | warning | error | failure
assert x > 0 report "x must be positive" severity error;
return value;                            -- in functions
proc_call(arg1, arg2);                   -- procedure call