Course Overview

What this VHDL course covers, how to use it, prerequisites.

A self-contained, hands-on course covering VHDL (VHSIC Hardware Description Language) for digital design and verification: language fundamentals, data types, concurrent and sequential statements, combinational and sequential logic, finite state machines, structural design, testbenches, VHDL-2008/2019 features, synthesis, FPGA architecture, timing, clock domain crossing, memories, arithmetic and DSP, standard interfaces (UART, SPI, I2C, AXI), verification methodologies (OSVVM, UVVM, VUnit, cocotb, formal), and complete FPGA projects. Every chapter has examples and exercises.

Course Map

Part I — Foundations Introduction to VHDL & Digital Design Tools & the FPGA/ASIC Design Flow

Your First Design: Entity & Architecture Lexical Elements, Libraries & Packages

Objects: Signals, Variables, Constants, Files Part II — Core Design Processes & Sequential Statements

Simulation Semantics: Delta Cycles, Signals vs Variables Combinational Logic Design Sequential Logic Design Finite State Machines

Structural Design: Components, Generics & Generate Subprograms: Functions & Procedures Packages & Libraries File I/O with TEXTIO

Part III — Advanced VHDL & FPGA Engineering Memories: RAM, ROM, FIFOs Arithmetic, Fixed Point & DSP

Synthesis: Inference, Coding for Hardware, Pitfalls FPGA Architecture & Resources

Timing: Constraints, Static Timing Analysis, Pipelining Clocks, Resets & Clock Domain Crossing

Communication Interfaces: UART, SPI, I2C, VGA On-Chip Buses: AXI4, AXI-Stream, Avalon, Wishbone

Advanced Verification: Self-Checking, OSVVM, UVVM, VUnit, cocotb Formal Verification & PSL

IP Integration, Mixed-Language Design & HLS Low Power, Reliability & ASIC Considerations Part IV — Projects & Real-World VHDL Complete FPGA Projects Designing a Simple CPU Best Practices & Coding Style

Appendices: Cheat Sheet, Keywords, Operators, Resources, Study Plan