Introduction to UVM

How the Universal Verification Methodology standardizes the layered testbench: components, sequences, phases, the factory and the configuration database.

UVM (IEEE 1800.2) is a free, open-source SystemVerilog class library and methodology used across the semiconductor industry. It turns the layered testbench into standard building blocks, so verification components written by one team (or bought as verification IP) plug into another team's environment.

The main concepts

drv = new("drv", this);

drv = adder_driver::type_id::create("drv", this);

Creating components with new() bypasses the factory, so tests can no longer override them. Always use type_id::create in UVM code.

What is the difference between an active and a passive agent?

An active agent has a sequencer and driver and drives the interface; a passive agent only has a monitor and observes it, e.g. when the interface is driven by another design block.

Why do UVM tests raise and drop objections?

run_phase ends when no component has an objection raised. Raising one before starting a sequence and dropping it afterwards keeps the simulation running exactly as long as the stimulus needs.