Strings & Formatting

The string type, its methods, comparisons and $sformatf for building messages.

Verilog stored text in bit vectors of fixed size. SystemVerilog's string type is a real string: dynamic length, comparison operators, methods and conversion to and from numbers. Testbenches use it for names, messages and logs.

Notes

s.substr(0, 4) // expecting 4 characters s.substr(0, 3) // characters 0..3 substr's second argument is the index of the last character, inclusive, not a length.

How do you build the string "id=7 addr=0x1F" from int id and logic [7:0] addr?

string s = $sformatf("id=%0d addr=0x%h", id, addr);