Interfaces & Modports

Bundle a bus into one port, give each side its own directions, and connect modules with a single line.

Real buses have many signals: valid, ready, data, last, user bits, plus clock and reset. In Verilog every module that uses the bus lists every signal as a port, and every instantiation connects every signal. An interface bundles them into one object; modports say which side drives what.

A valid/ready stream

counter_source sends 1, 2, 3, ... and only moves to the next word after the current one was accepted.

adder_sink is ready every other clock, which creates back-pressure: the source must hold its data until ready.

link creates one stream_if instance and connects both modules with a single port each.

Interfaces in verification

module sink (stream_if s); // no modport module sink (stream_if.sink s);

Without a modport every signal is accessible in both directions, so a module can accidentally drive a signal it should only read. Modports let the compiler check directions.

When does a transfer happen on a valid/ready interface?

On a clock edge where both valid and ready are high. The source must keep valid and data stable until that happens.

What is a virtual interface?

A variable that holds a reference to an interface instance, so class-based testbench code (which cannot have ports) can access the DUT's signals.