Design for Test

Scan, ATPG, BIST and silicon test. Making chips testable after manufacturing: fault models, scan chains, ATPG, memory and logic BIST, boundary scan and yield.

• Design for Testability (DFT) — Manufactured chips must be tested for defects. Learn fault models (stuck-at, transition, bridging), controllability and observability, scan chains and scan insertion, ATPG and fault coverage, test time and compression, memory BIST and logic BIST, JTAG boundary scan (IEEE 1149.1), and defect level (DPPM).