Synthesis & Timing

From RTL to gates, and making them fast enough. Logic synthesis with standard-cell libraries and constraints, then static timing analysis: setup, hold, slack, corners and timing closure.

• ASIC Flow & Logic Synthesis — From RTL to gates for a custom chip. Learn what logic synthesis does (translation, optimisation, technology mapping), SDC constraints, synthesis reports (area, timing, power), gate-level netlists and equivalence checking, ASIC vs FPGA economics (NRE vs unit cost), and foundry/PDK concepts.
• Static Timing Analysis — Static timing analysis (STA) verifies that every path meets timing without simulation. Learn timing paths, arrival and required times, setup and hold checks and slack, clock skew, jitter and uncertainty, false and multicycle paths, PVT corners and OCV, and how to fix violations.