Sign-off: IR Drop, EM, Crosstalk & Antenna

Before tape-out a chip must pass every sign-off check. Learn static and dynamic IR drop, electromigration (EM) and Black's equation, crosstalk delay and glitch, antenna effect, multi-corner multi-mode (MCMM) STA, ECOs, the final checklist (STA, LEC, DRC, LVS, IR/EM, SI) and GDSII tape-out — with an IR-drop calculator for a power rail.

A routed design can still fail in silicon: supply voltage may sag where many cells switch (IR drop), wires may wear out from current (electromigration), neighbouring wires may disturb each other (crosstalk), and plasma during fabrication can damage gates (antenna).

Sign-off analysis checks all of these across every process, voltage and temperature corner and every operating mode. Only when all checks are clean does the design go to the foundry as GDSII/OASIS — the tape-out.

An analogy

Sign-off is the final safety inspection of a building: the electrical wiring can carry the load (EM), the voltage holds up when everything is switched on (IR), neighbours don't interfere (crosstalk), and construction didn't damage anything (antenna).

IR drop

Current through the resistance of the power grid lowers the voltage reaching cells, making them slower (and ground bounce raises VSS). Static IR uses average currents; dynamic IR simulates simultaneous switching and is usually much worse locally. Fixes: more straps and vias, decoupling capacitors, spreading high-activity cells, and staggering clock-gating enables.

Electromigration

High current density pushes metal atoms along a wire, forming voids (opens) and hillocks (shorts) over years. Black's equation shows lifetime drops steeply with current density and temperature. Power nets see DC EM; signal and clock nets see AC (RMS/peak) limits. Fixes: wider wires, more vias, lower drive strength, NDRs.

Crosstalk and antenna

Two classic signal-integrity and manufacturing problems:

MCMM sign-off and tape-out

Timing is signed off in many scenarios: corners (SS/FF/TT × voltages × temperatures × RC extraction corners) and modes (functional, test, low-power). ECOs fix late violations with minimal changes (often metal-only, reusing spare cells). The final checklist: STA all scenarios, LEC RTL↔netlist, DRC/LVS/antenna/density clean, IR/EM clean, ESD/latch-up checks, then GDSII/OASIS stream-out and the foundry's tape-out review.

Formulas

Worked example: Static IR

Given: Grid resistance 0.05 Ω to a block drawing 2 A

Find: IR drop.

Answer: 100 mV (10% of 1.0 V — at the limit)

Worked example: Crosstalk glitch

Given: C_c = 20 fF, C_g = 30 fF

Find: Glitch on a floating victim.

Answer: 0.4·V_DD — dangerous; a driven victim sees much less

Worked example: EM lifetime

Given: Black's n = 2, current density doubled

Find: Lifetime change.

Answer: Lifetime drops to 1/4

IR drop along a power rail

# IR drop along a power rail fed from one end: N cells, each drawing I,
# rail segment resistance R between cells.
VDD, N, I, R = 1.0, 10, 5e-3, 0.5          # V, cells, A per cell, ohm per segment

v = VDD
worst = VDD
for k in range(N):
    current_in_segment = (N - k) * I         # current still flowing downstream
    v -= current_in_segment * R
    worst = min(worst, v)
drop = VDD - worst
print(f"worst-case rail voltage {worst*1000:.1f} mV, IR drop {drop*1000:.1f} mV ({drop/VDD*100:.1f}% of VDD)")

# Feeding the rail from both ends roughly quarters the worst drop
half = N // 2
v2 = VDD - sum((half - k) * I * R for k in range(half))
print(f"fed from both ends: IR drop {(VDD - v2)*1000:.1f} mV")
# worst-case rail voltage 862.5 mV, IR drop 137.5 mV (13.7% of VDD)
# fed from both ends: IR drop 37.5 mV

The first segment carries all the current, so the drop accumulates toward the far end. Feeding from both ends (more straps) cuts it from 137.5 to 37.5 mV — exactly why power grids are meshes with frequent straps.

Common mistakes

Applications

Key takeaways

Going further