Physical Design

Turning a netlist into manufacturable layout. Learn floorplanning, power planning and IR drop, placement and utilisation, clock-tree synthesis, routing and congestion, wire delay (Elmore), parasitic extraction, physical verification (DRC, LVS, antenna), yield and dies per wafer.

Physical design places millions of cells and routes kilometres of microscopic wires across a dozen metal layers, while meeting timing, power integrity and thousands of manufacturing rules. The output (GDSII/OASIS) goes to the foundry for masks.

An analogy

Physical design is urban planning for transistors: zoning (floorplan), utilities (power grid), traffic (routing), and time zones (clock tree) must all work together.

Floorplan and placement

Define die size, place I/Os, hard macros (memories, analog) and power grid, then place standard cells in rows at 60–80 % utilisation, optimising wirelength and timing.

Clock tree synthesis

Build a balanced buffer tree (or mesh) delivering the clock to every flip-flop with low skew and controlled transition. Clock power can be 30–40 % of dynamic power.

Routing

Global then detailed routing on multiple metal layers; upper layers are thicker for power and long wires. Congestion, crosstalk and electromigration must be managed; long wires need repeaters (delay grows with L²).

Sign-off and yield

Parasitic extraction (SPEF) → STA; IR drop and EM analysis; DRC (design rules), LVS (layout vs schematic), antenna, density and DFM checks. Yield falls exponentially with die area — large dies use redundancy or chiplets.

Formulas

• Elmore wire delay: t ≈ 0.5 r c L²
• IR drop: ΔV = I × R_grid, I = P/V
• Dies per wafer: DPW ≈ π(d/2)²/A − πd/√(2A)
• Yield (Poisson): Y = e^(−D₀ A)

Worked example: Wire delay

Given: r = 0.5 Ω/µm, c = 0.2 fF/µm, L = 1 mm

Find: Elmore delay.

• t = 0.5 × 0.5 × 0.2 × 10⁻¹⁵ × (1000)² = 50 ps

Answer: 50 ps (4× if length doubles — insert repeaters)

Worked example: Good dies per wafer

Given: 300 mm wafer, 100 mm² die, D₀ = 0.1/cm²

Find: Good dies.

• DPW = 706.9 − 66.6 = 640
• Y = e^(−0.1) = 0.905
• Good ≈ 579

Answer: ≈ 579 good dies

Common mistakes

• Wrong: Over-packing cells (utilisation too high). — Right: Leave room for routing and buffers.
• Wrong: Weak power grid. — Right: Plan grid for peak current; check IR drop early.

Applications

• SoC implementation: Innovus/ICC2 place-and-route.
• Chiplets: Smaller dies for better yield.
• Power integrity: IR/EM sign-off for high-current chips.

Key takeaways

• Floorplan → power → place → CTS → route → sign-off.
• Wire delay ∝ L² — use repeaters.
• Check IR drop and EM.
• Yield = e^(−D₀A).

Going further

• Multi-patterning: Coloring for sub-10 nm lithography.
• Backside power delivery: Power rails under transistors.
• 3D ICs: Hybrid bonding and TSVs.