Latches & Flip-Flops

Sequential circuits remember. Learn the SR latch, gated D latch, edge-triggered D, JK and T flip-flops, characteristic tables and equations, setup, hold and clock-to-Q times, maximum clock frequency, metastability and synchronisers.

Adding feedback to gates creates memory. Flip-flops store one bit and update it only on a clock edge, giving synchronous circuits their predictable timing. Every register, counter and state machine is built from flip-flops.

An analogy

A flip-flop is like a camera that only takes a picture when the shutter clicks (clock edge): whatever the input is at that instant is stored until the next click.

Latches

Cross-coupled NOR (or NAND) gates form an SR latch: S sets Q = 1, R resets Q = 0, S = R = 1 is forbidden. A gated D latch is transparent while enable is high.

Edge-triggered flip-flops

A master–slave pair of latches samples D only at the clock edge. D is the standard in modern design; JK (toggle when J = K = 1) and T (toggle) appear in counters and textbooks.

Timing

Data must be stable t_su before and t_h after the edge. The longest register-to-register path sets the minimum clock period; hold violations come from paths that are too fast.

Metastability

Violating setup/hold (e.g. asynchronous inputs) can leave a flip-flop in an in-between state for an unpredictable time. Two- or three-stage synchronisers make failure probability negligible (MTBF of years).

Formulas

• D flip-flop: Q⁺ = D
• JK flip-flop: Q⁺ = JQ′ + K′Q
• T flip-flop: Q⁺ = T ⊕ Q
• Timing constraint: T_clk ≥ t_cq + t_logic + t_su + t_skew
• Hold constraint: t_cq + t_logic,min ≥ t_h + t_skew

Worked example: Maximum clock frequency

Given: t_cq = 1 ns, logic 5 ns, t_su = 0.5 ns

Find: f_max.

• T = 1 + 5 + 0.5 = 6.5 ns
• f_max = 153.8 MHz

Answer: ≈ 154 MHz

Worked example: JK toggle

Given: J = K = 1, Q = 0

Find: Q after 3 clock edges.

• Toggle each edge: 1, 0, 1

Answer: Q = 1

D flip-flop with asynchronous reset

module dff (input clk, rst_n, d, output reg q);
  always @(posedge clk or negedge rst_n)
    if (!rst_n) q <= 1'b0;     // asynchronous, active-low reset
    else        q <= d;        // capture D on the rising edge
endmodule

// Two-flip-flop synchroniser for an asynchronous input
module sync2 (input clk, async_in, output reg sync_out);
  reg meta;
  always @(posedge clk) begin
    meta     <= async_in;
    sync_out <= meta;
  end
endmodule

Non-blocking assignments (<=) model registers updating together on the clock edge. The synchroniser gives a metastable first stage a full clock period to resolve.

Common mistakes

• Wrong: Using latches unintentionally in HDL. — Right: Assign all outputs in combinational blocks.
• Wrong: Feeding asynchronous inputs straight into logic. — Right: Synchronise with two flip-flops first.

Applications

• Registers: Store data between pipeline stages.
• State machines: Hold the current state.
• Synchronisers: Safely bring in asynchronous signals.

Key takeaways

• Latches are level-sensitive; flip-flops edge-triggered.
• D: Q⁺ = D; JK; T toggles.
• T_clk ≥ t_cq + t_logic + t_su + skew.
• Synchronise asynchronous inputs.

Going further

• Clock domain crossing: Handshakes and async FIFOs.
• Retiming: Moving registers to balance paths.
• Low-power flops: Clock gating and retention.