Fabrication & Layout

From sand to wafers, masks and layout rules. How chips are manufactured — wafers, oxidation, lithography, etching, doping, deposition, CMP and interconnect — then CMOS technology and layout, design rules, and the physical-verification checks (DRC, LVS, extraction) that connect layout to silicon.

• IC Fabrication Process — How a design becomes silicon. Learn wafer preparation, oxidation, photolithography (resolution, EUV), etching, ion implantation and annealing, deposition (CVD, ALD, PVD), CMP, the front-end (transistor) and back-end (copper interconnect) flow, process nodes, masks, and wafer economics — dies per wafer and yield.
• CMOS Technology — CMOS is the technology behind nearly all digital chips. Learn NMOS/PMOS switches, the CMOS inverter and its voltage-transfer curve, static CMOS gates (pull-up/pull-down networks), switching delay, dynamic and leakage power, fabrication steps, and scaling from micrometres to FinFET and gate-all-around nodes.
• Layout, DRC, LVS & Parasitic Extraction — Before tape-out, the layout must be manufacturable and must match the schematic. Learn layers and stick diagrams, standard-cell layout, design rules and DRC, layout-versus-schematic (LVS), antenna and density checks, parasitic extraction (R and C of wires), wire RC delay, and how sign-off tools (Calibre, Pegasus, KLayout, Magic) are used.