CMOS Digital Circuits

Inverters, gates, datapaths, memories and power. Transistor-level digital design: the CMOS inverter, static gates and logical effort, digital IC design styles, adders and multipliers, SRAM memories and low-power design techniques.

• The CMOS Inverter: VTC, Noise Margins, Delay & Power — The inverter is the atom of digital CMOS. Learn its operation, the voltage-transfer characteristic (VTC), switching threshold and PMOS/NMOS sizing, noise margins, propagation delay from R·C, rise/fall times, fan-out, and the three kinds of power — dynamic, short-circuit and leakage. Every other gate is analysed the same way.
• Static CMOS Gates, Sizing & Logical Effort — How to build and size fast CMOS logic. Learn pull-up/pull-down networks and duality, NAND vs NOR, transistor sizing for equal drive, the logical-effort delay model (d = gh + p), path effort, the optimum number of stages and stage effort ≈ 4, branching, and how to size a whole path by hand — with a Python calculator.
• Digital IC Design — How digital chips are designed: specification, architecture, RTL, verification, synthesis, physical design and sign-off. Learn standard cells and libraries, design metrics (performance, power, area — PPA), gate-count and area estimation, clocking, low-power techniques and the front-end/back-end split.
• Arithmetic Circuits: Adders & Multipliers — Datapaths are built from adders and multipliers. Learn half and full adders, ripple-carry adders, generate/propagate, carry-lookahead, carry-select and parallel-prefix adders (Kogge-Stone, Brent-Kung), subtraction and overflow, array and Wallace-tree multipliers and Booth encoding — with Verilog that is formally proven correct.
• SRAM & Memory Design — Memories fill most of a modern SoC's area. Learn the 6T SRAM cell, read and write operations, read stability and writability (cell ratio, pull-up ratio), static noise margin, array organisation (rows, columns, decoders, sense amplifiers), bitline timing, memory compilers, register files, DRAM and non-volatile memories, and how RTL infers memories.
• Low-Power VLSI Design — Power limits every modern chip, from phones to data-centre GPUs. Learn the dynamic/short-circuit/leakage power equation, clock gating (with a real ICG cell), operand isolation, multi-V_t and multi-V_DD design, power gating with retention, DVFS, UPF power intent, and how power is estimated from activity (SAIF/VCD).