Processor Architecture

How a CPU works inside: the fetch–decode–execute cycle, ALU, registers, program counter, control unit and buses; von Neumann vs Harvard architectures; CISC vs RISC; clock rate, CPI and MIPS; pipelining and hazards; and the memory hierarchy with caches.

Every processor — from an 8-bit 8085 to a smartphone's ARM cores — repeats the same loop: fetch an instruction from memory, decode it, execute it, and store the result. Architecture is how that loop is organised to run fast and efficiently.

An analogy

A CPU is like a chef following a recipe: fetch the next line (instruction), understand it (decode), do it (execute), and keep ingredients close at hand in small bowls (registers) and the fridge (cache) instead of the supermarket (main memory).

Building blocks

ALU (arithmetic and logic), register file (fast storage), control unit (decodes instructions and generates control signals), PC (address of next instruction), and buses: address bus (where), data bus (what), control bus (read/write/interrupt).

Architectures

Von Neumann: shared memory for code and data (simple, bottleneck). Harvard: separate instruction and data memories (MCUs, DSPs). CISC (x86): complex, variable-length instructions. RISC (ARM, RISC-V): simple, fixed-length load/store instructions, easy to pipeline.

Pipelining

Classic 5-stage pipeline: fetch, decode, execute, memory, write-back. Hazards — structural, data (use forwarding/stalls) and control (branch prediction) — reduce ideal speed-up.

Memory hierarchy

Registers → L1 → L2 → L3 caches → DRAM → storage; each level larger and slower. Caches exploit temporal and spatial locality. Superscalar, out-of-order, multicore and SIMD extend performance further.

Formulas

• Execution time: T = instructions × CPI / f
• MIPS: MIPS = f (MHz) / CPI
• Pipeline speed-up: S = n k / (k + n − 1) (k stages, n instructions)
• Average memory access time: AMAT = hit time + miss rate × miss penalty

Worked example: Execution time

Given: 10⁶ instructions, CPI 1.5, 100 MHz

Find: Time and MIPS.

• T = 10⁶ × 1.5/10⁸ = 15 ms
• MIPS = 100/1.5 = 66.7

Answer: 15 ms, 66.7 MIPS

Worked example: Cache effect

Given: Hit 1 cycle, miss rate 5 %, penalty 50 cycles

Find: AMAT.

• AMAT = 1 + 0.05 × 50 = 3.5 cycles

Answer: 3.5 cycles (3.5× slower than always hitting)

Common mistakes

• Wrong: Comparing CPUs by clock speed only. — Right: Performance = f/CPI × instructions — architecture matters.
• Wrong: Ignoring memory latency. — Right: Cache misses often dominate run time.

Applications

• Processor selection: Compare MIPS, power and architecture.
• Performance tuning: Cache-aware code and data layout.
• Embedded design: Harvard MCUs for deterministic timing.

Key takeaways

• Fetch–decode–execute.
• T = N × CPI/f.
• Pipelining and caches boost speed.
• RISC vs CISC; von Neumann vs Harvard.

Going further

• Branch prediction: Dynamic predictors reduce control hazards.
• Out-of-order execution: Tomasulo and reorder buffers.
• Cache coherence: MESI in multicore systems.