Synthesis

24.1 What synthesizes and what doesn't

concurrent assignments, processes with clock edges wait for, after delays (ignored)

if, case, for loops with static bounds while loops with dynamic bounds (mostly), file I/O at runtime integer (with ranges), std_logic, numeric_std, enums, records, arrays

real signals, access types, time arithmetic functions, procedures without wait textio (except ROM init at elaboration) generics, generate

assert/report (ignored, or used as checks by some tools) initial values on signals (FPGA) initial values (ASIC)

24.2 Inference templates

Synthesis recognizes patterns:

if rising_edge(clk) incomplete combinational if latch (avoid!) case/with select adders with carry chains array signal + clocked write/read block/distributed RAM constant array indexed ROM (LUTs or BRAM) shift register without reset SRL primitives (Xilinx SRL16/32) 'Z' assignment on inout tri-state buffers (top-level I/O only in FPGAs) enumerated state signal FSM extraction & re-encoding

24.3 Synthesis rules of thumb

One clock edge per process; use rising_edge(clk).

Separate combinational and sequential logic clearly.

Avoid latches: default assignments; complete case/if.

Never use a signal as a clock unless it comes from a clock buffer / PLL. No gated clocks — use clock enables.

Don't rely on initial values for ASICs; use resets (only where needed — fewer resets = better FPGA utilization).

Keep combinational paths short between registers (timing).

Avoid combinational loops.

Use integer ranges or sized vectors to control widths.

Prefer synchronous design; register module outputs.

Avoid tri-states inside the FPGA fabric (use muxes).

Read the synthesis report and warnings (latches, unconnected ports, trimmed logic, multi-driven nets).

24.4 Common synthesis warnings & meanings

*"Latch inferred for signal X"* — missing assignment in a combinational path.

*"Signal X is not in the sensitivity list"* — simulation/synthesis mismatch (use process(all)).

*"Multi-driven net"* — assigned in two processes.

*"Signal X is unused / trimmed"* — logic optimized away (check if intentional).

*"Combinational loop detected"*.

*"Truncated value"* — width mismatch.

24.5 Simulation vs synthesis mismatches

Incomplete sensitivity lists, after delays, initial values (ASIC), 'X'/'-' handling, full/parallel case assumptions, reading uninitialized variables. Run post-synthesis/post-implementation simulation for critical designs.