Structural Design

No component declaration needed; architecture optional.

15.1 Component instantiation

architecture structural of full_adder is
  component half_adder is
    port (a, b : in std_logic; s, c : out std_logic);
  end component;
  signal s1, c1, c2 : std_logic;
begin
  ha1 : half_adder port map (a => a, b => b, s => s1, c => c1);       -- named association (preferred)
  ha2 : half_adder port map (s1, cin, sum, c2);                        -- positional association
  cout <= c1 or c2;
end architecture;

15.2 Direct entity instantiation (VHDL-93+, preferred)

No component declaration needed; architecture optional.

u_ha1 : entity work.half_adder(rtl)
  port map (a => a, b => b, s => s1, c => c1);

15.3 Generics (parameters)

Port map extras: open for unused outputs, constants on inputs (en => '1'), expressions in port maps (VHDL-2008).

entity counter is
  generic (
    WIDTH : positive := 8;
    MAX   : natural  := 255);
  port (
    clk, rst : in  std_logic;
    q        : out std_logic_vector(WIDTH-1 downto 0));
end entity;

u_cnt : entity work.counter
  generic map (WIDTH => 16, MAX => 49_999)
  port map (clk => clk, rst => rst, q => count16);

15.4 Generate statements

-- for-generate: replicate hardware
gen_regs : for i in 0 to N-1 generate
  u_ff : entity work.dff port map (clk => clk, d => d(i), q => q(i));
end generate;

-- if-generate: conditional hardware
gen_pipe : if PIPELINED generate
  process (clk) begin if rising_edge(clk) then y <= x; end if; end process;
else generate                       -- VHDL-2008 else/elsif branches
  y <= x;
end generate;

-- case-generate (VHDL-2008)
gen_impl : case IMPL generate
  when "fast" => u : entity work.adder_cla port map (...);
  when others => u : entity work.adder_rca port map (...);
end generate;

15.5 Configurations

Used to swap implementations (e.g., behavioral models vs gate-level netlists) without editing the design.

configuration cfg_top of top is
  for structural
    for u_alu : alu use entity work.alu(fast); end for;
  end for;
end configuration;