Simulation Semantics

Delta cycles model "zero-delay" ordering of concurrent logic deterministically.

11.1 Events, transactions & the simulation cycle

Signals updated → events on signals that changed value.

Processes sensitive to those signals resume and run until they suspend.

Their signal assignments are scheduled (not immediate).

If scheduled for the current time → a new delta cycle (zero simulated time) begins.

When no more deltas remain, simulated time advances to the next scheduled event.

Delta cycles model "zero-delay" ordering of concurrent logic deterministically.

11.2 Signals vs variables — the most important distinction

end of process / after delta inside the process wire or register intermediate logic (or register if read before written in a clocked process)

Last assignment wins: if a process assigns a signal several times, only the last scheduled value takes effect — handy for default assignments:

process (clk)
  variable v : integer := 0;
begin
  if rising_edge(clk) then
    -- Signals: a, b updated at the END of the process (after this delta)
    a <= 1;
    b <= a;          -- b gets the OLD value of a  → creates two registers in series
    -- Variables: updated immediately
    v := 1;
    c <= v;          -- c gets 1
  end if;
end process;

process (all)
begin
  y <= '0';                    -- default
  if cond then y <= '1'; end if;
end process;

11.3 Drivers & resolution

Each process (or concurrent assignment) that assigns a signal creates a driver. Multiple drivers on a std_logic signal are resolved; on std_ulogic they are a compile error — useful to catch mistakes. Only tri-state buses should legitimately have multiple drivers.

11.4 Initial values

Signals start as 'U' (std_logic) or type'left unless initialized. Initial values are honored in simulation and by most FPGA synthesis tools (power-up state), but not in ASICs — use resets for guaranteed initialization.