Your First Design: Entity & Architecture

3.1 A 2-input AND gate

library ieee;
use ieee.std_logic_1164.all;

-- Entity: the external interface (ports)
entity and_gate is
  port (
    a : in  std_logic;
    b : in  std_logic;
    y : out std_logic
  );
end entity and_gate;

-- Architecture: the internal behavior/structure
architecture rtl of and_gate is
begin
  y <= a and b;        -- concurrent signal assignment
end architecture rtl;

3.2 Simulating with GHDL

With NVC: nvc --std=2008 -a and_gate.vhd and_gate_tb.vhd -e and_gate_tb -r --wave.

library ieee;
use ieee.std_logic_1164.all;

entity and_gate_tb is
end entity;                     -- testbenches have no ports

architecture sim of and_gate_tb is
  signal a, b, y : std_logic := '0';
begin
  dut : entity work.and_gate port map (a => a, b => b, y => y);

  stimulus : process
  begin
    a <= '0'; b <= '0'; wait for 10 ns; assert y = '0' report "0 and 0 failed" severity error;
    a <= '0'; b <= '1'; wait for 10 ns; assert y = '0' report "0 and 1 failed" severity error;
    a <= '1'; b <= '0'; wait for 10 ns; assert y = '0' report "1 and 0 failed" severity error;
    a <= '1'; b <= '1'; wait for 10 ns; assert y = '1' report "1 and 1 failed" severity error;
    report "Test complete";
    wait;                       -- stop this process forever
  end process;
end architecture sim;

ghdl -a --std=08 and_gate.vhd and_gate_tb.vhd   # analyze (compile)
ghdl -e --std=08 and_gate_tb                     # elaborate
ghdl -r --std=08 and_gate_tb --wave=wave.ghw     # run, dump waveform
gtkwave wave.ghw

3.3 Design units

interface: ports & generics implementation (an entity can have several) shared declarations (types, constants, subprogram declarations) package body binds entities to architectures/components context (2008) reusable group of library/use clauses

3.4 Port modes

input (read only) output (readable inside since VHDL-2008) bidirectional (tri-state buses, top-level pins) output that can be read internally (avoid; use out + 2008)

3.5 Multiple architectures

Select one with entity work.and_gate(behavioral) or a configuration.

architecture behavioral of and_gate is
begin
  process (a, b)
  begin
    if a = '1' and b = '1' then y <= '1'; else y <= '0'; end if;
  end process;
end architecture;