Synthesis: From Verilog to Gates

What synthesis does, the synthesizable subset, and how to read a synthesis report.

Synthesis reads your RTL, works out the logic functions and storage it describes, optimizes them, and maps them onto the cells available in the target: standard cells for a chip, look-up tables, flip-flops, carry chains, DSP blocks and block RAM for an FPGA. Throughout this course you have seen real Yosys results; this lesson explains how to read them and what code synthesis accepts.

Reading a synthesis report

for (i = 0; i < n; i = i + 1) // n is a signal for (i = 0; i < MAX; i = i + 1) if (i < n)...

Synthesis unrolls loops, so the bound must be a constant. Loop to the maximum and use a condition inside.

Name four Verilog constructs that synthesis ignores or rejects.

Delays (#), $display/$finish and other system tasks, real-number arithmetic, === / !==, fork/join, wait, and loops with non-constant bounds.

Your synthesis report shows 0 flip-flops for a design that should count. What happened?

Most likely the logic was optimized away: an output is not connected, the clock or enable is constant, or the counter value never reaches an output — synthesis removes logic that does not affect any output.