FPGA & ASIC Design Flow

From RTL to a programmed FPGA or a manufactured chip: constraints, place and route, timing closure and on-chip debugging.

Writing correct RTL is only the first part of building hardware. The same Verilog goes through a flow that maps it onto physical resources and proves it meets timing. The flows for FPGAs and ASICs share the front end and differ in the back end.

Timing closure

No clock constraint in the project create_clock -period 10.000 -name sys_clk [get_ports clk]

Without a clock constraint the timing analysis has nothing to check against, so the tool reports no timing problems even if the design cannot run at your clock speed.

What does negative slack mean?

A path takes longer than the time allowed by the clock (minus setup): the design will not work reliably at that frequency. Slack must be zero or positive on every path.

What is pipelining and what does it cost?

Inserting registers into a long combinational path so each stage is shorter, allowing a faster clock. It costs extra flip-flops and adds latency (the result appears more clocks later).