NEON SIMD

Vector registers and lanes: process 4, 8 or 16 values with one instruction.

NEON (Advanced SIMD) lets one instruction operate on several values packed into a 128-bit register: four floats, eight 16-bit integers or sixteen bytes. It is how phones decode video, filter audio and run machine-learning kernels efficiently.

Vector arithmetic

ld1 {v0.4s}, [x0] loads four 32-bit floats into one vector register.

fadd v2.4s, v0.4s, v1.4s adds all four lanes at once.

fmla multiplies and accumulates four lanes per instruction; faddp adds lanes pairwise to reduce the vector to one sum.

uqadd adds eight bytes with saturation: 200 + 100 becomes 255 instead of wrapping to 44.

Using NEON in practice

Processing a length that is not a multiple of the vector width with only the vector loop

Handle the remaining elements with a scalar tail loop The vector loop reads and writes whole vectors; leftover elements must be processed separately (or the buffers padded).

What does the suffix .8h mean on a NEON register?

The 128-bit register is treated as eight lanes of 16-bit halfwords.